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hwasan: Compatibility fixes for short granules.
We can't use short granules with stack instrumentation when targeting older API levels because the rest of the system won't understand the short granule tags stored in shadow memory. Moreover, we need to be able to let old binaries (which won't understand short granule tags) run on a new system that supports short granule tags. Such binaries will call the __hwasan_tag_mismatch function when their outlined checks fail. We can compensate for the binary's lack of support for short granules by implementing the short granule part of the check in the __hwasan_tag_mismatch function. Unfortunately we can't do anything about inline checks, but I don't believe that we can generate these by default on aarch64, nor did we do so when the ABI was fixed. A new function, __hwasan_tag_mismatch_v2, is introduced that lets code targeting the new runtime avoid redoing the short granule check. Because tag mismatches are rare this isn't important from a performance perspective; the main benefit is that it introduces a symbol dependency that prevents binaries targeting the new runtime from running on older (i.e. incompatible) runtimes. Differential Revision: https://reviews.llvm.org/D68059 llvm-svn: 373035
This commit is contained in:
Peter Collingbourne
parent
cfc930fd01
commit
855343fa29
@ -1136,6 +1136,8 @@ def int_load_relative: Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_anyint_ty],
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def int_hwasan_check_memaccess :
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Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], [IntrInaccessibleMemOnly, ImmArg<2>]>;
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def int_hwasan_check_memaccess_shortgranules :
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Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty, llvm_i32_ty], [IntrInaccessibleMemOnly, ImmArg<2>]>;
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// Xray intrinsics
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//===----------------------------------------------------------------------===//
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@ -99,7 +99,7 @@ public:
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void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI);
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void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI);
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std::map<std::pair<unsigned, uint32_t>, MCSymbol *> HwasanMemaccessSymbols;
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std::map<std::tuple<unsigned, bool, uint32_t>, MCSymbol *> HwasanMemaccessSymbols;
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void LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI);
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void EmitHwasanMemaccessSymbols(Module &M);
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@ -237,8 +237,10 @@ void AArch64AsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
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void AArch64AsmPrinter::LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
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Register Reg = MI.getOperand(0).getReg();
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bool IsShort =
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MI.getOpcode() == AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES;
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uint32_t AccessInfo = MI.getOperand(1).getImm();
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MCSymbol *&Sym = HwasanMemaccessSymbols[{Reg, AccessInfo}];
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MCSymbol *&Sym = HwasanMemaccessSymbols[{Reg, IsShort, AccessInfo}];
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if (!Sym) {
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// FIXME: Make this work on non-ELF.
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if (!TM.getTargetTriple().isOSBinFormatELF())
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@ -246,6 +248,8 @@ void AArch64AsmPrinter::LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
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std::string SymName = "__hwasan_check_x" + utostr(Reg - AArch64::X0) + "_" +
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utostr(AccessInfo);
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if (IsShort)
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SymName += "_short";
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Sym = OutContext.getOrCreateSymbol(SymName);
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}
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@ -263,15 +267,22 @@ void AArch64AsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
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std::unique_ptr<MCSubtargetInfo> STI(
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TM.getTarget().createMCSubtargetInfo(TT.str(), "", ""));
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MCSymbol *HwasanTagMismatchSym =
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MCSymbol *HwasanTagMismatchV1Sym =
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OutContext.getOrCreateSymbol("__hwasan_tag_mismatch");
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MCSymbol *HwasanTagMismatchV2Sym =
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OutContext.getOrCreateSymbol("__hwasan_tag_mismatch_v2");
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const MCSymbolRefExpr *HwasanTagMismatchRef =
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MCSymbolRefExpr::create(HwasanTagMismatchSym, OutContext);
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const MCSymbolRefExpr *HwasanTagMismatchV1Ref =
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MCSymbolRefExpr::create(HwasanTagMismatchV1Sym, OutContext);
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const MCSymbolRefExpr *HwasanTagMismatchV2Ref =
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MCSymbolRefExpr::create(HwasanTagMismatchV2Sym, OutContext);
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for (auto &P : HwasanMemaccessSymbols) {
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unsigned Reg = P.first.first;
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uint32_t AccessInfo = P.first.second;
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unsigned Reg = std::get<0>(P.first);
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bool IsShort = std::get<1>(P.first);
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uint32_t AccessInfo = std::get<2>(P.first);
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const MCSymbolRefExpr *HwasanTagMismatchRef =
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IsShort ? HwasanTagMismatchV2Ref : HwasanTagMismatchV1Ref;
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MCSymbol *Sym = P.second;
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OutStreamer->SwitchSection(OutContext.getELFSection(
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@ -304,82 +315,86 @@ void AArch64AsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
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.addReg(Reg)
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
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*STI);
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MCSymbol *HandlePartialSym = OutContext.createTempSymbol();
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MCSymbol *HandleMismatchOrPartialSym = OutContext.createTempSymbol();
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::Bcc)
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.addImm(AArch64CC::NE)
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.addExpr(MCSymbolRefExpr::create(HandlePartialSym, OutContext)),
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.addExpr(MCSymbolRefExpr::create(HandleMismatchOrPartialSym,
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OutContext)),
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*STI);
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MCSymbol *ReturnSym = OutContext.createTempSymbol();
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OutStreamer->EmitLabel(ReturnSym);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::RET).addReg(AArch64::LR), *STI);
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OutStreamer->EmitLabel(HandleMismatchOrPartialSym);
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OutStreamer->EmitLabel(HandlePartialSym);
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OutStreamer->EmitInstruction(MCInstBuilder(AArch64::SUBSWri)
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.addReg(AArch64::WZR)
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.addReg(AArch64::W16)
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.addImm(15)
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.addImm(0),
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*STI);
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MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::Bcc)
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.addImm(AArch64CC::HI)
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.addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::ANDXri)
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.addReg(AArch64::X17)
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.addReg(Reg)
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.addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)),
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*STI);
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unsigned Size = 1 << (AccessInfo & 0xf);
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if (Size != 1)
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OutStreamer->EmitInstruction(MCInstBuilder(AArch64::ADDXri)
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.addReg(AArch64::X17)
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.addReg(AArch64::X17)
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.addImm(Size - 1)
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if (IsShort) {
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OutStreamer->EmitInstruction(MCInstBuilder(AArch64::SUBSWri)
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.addReg(AArch64::WZR)
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.addReg(AArch64::W16)
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.addImm(15)
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.addImm(0),
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*STI);
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OutStreamer->EmitInstruction(MCInstBuilder(AArch64::SUBSWrs)
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.addReg(AArch64::WZR)
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.addReg(AArch64::W16)
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.addReg(AArch64::W17)
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.addImm(0),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::Bcc)
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.addImm(AArch64CC::LS)
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.addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
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*STI);
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MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::Bcc)
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.addImm(AArch64CC::HI)
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.addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::ORRXri)
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.addReg(AArch64::X16)
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.addReg(Reg)
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.addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)),
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*STI);
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OutStreamer->EmitInstruction(MCInstBuilder(AArch64::LDRBBui)
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.addReg(AArch64::W16)
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.addReg(AArch64::X16)
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.addImm(0),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::SUBSXrs)
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.addReg(AArch64::XZR)
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.addReg(AArch64::X16)
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.addReg(Reg)
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::Bcc)
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.addImm(AArch64CC::EQ)
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.addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::ANDXri)
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.addReg(AArch64::X17)
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.addReg(Reg)
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.addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)),
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*STI);
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unsigned Size = 1 << (AccessInfo & 0xf);
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if (Size != 1)
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OutStreamer->EmitInstruction(MCInstBuilder(AArch64::ADDXri)
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.addReg(AArch64::X17)
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.addReg(AArch64::X17)
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.addImm(Size - 1)
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.addImm(0),
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*STI);
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OutStreamer->EmitInstruction(MCInstBuilder(AArch64::SUBSWrs)
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.addReg(AArch64::WZR)
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.addReg(AArch64::W16)
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.addReg(AArch64::W17)
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.addImm(0),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::Bcc)
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.addImm(AArch64CC::LS)
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.addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::ORRXri)
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.addReg(AArch64::X16)
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.addReg(Reg)
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.addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)),
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*STI);
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OutStreamer->EmitInstruction(MCInstBuilder(AArch64::LDRBBui)
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.addReg(AArch64::W16)
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.addReg(AArch64::X16)
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.addImm(0),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::SUBSXrs)
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.addReg(AArch64::XZR)
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.addReg(AArch64::X16)
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.addReg(Reg)
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.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::Bcc)
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.addImm(AArch64CC::EQ)
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.addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)),
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*STI);
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OutStreamer->EmitLabel(HandleMismatchSym);
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}
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OutStreamer->EmitLabel(HandleMismatchSym);
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OutStreamer->EmitInstruction(MCInstBuilder(AArch64::STPXpre)
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.addReg(AArch64::SP)
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.addReg(AArch64::X0)
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@ -414,16 +429,16 @@ void AArch64AsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
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MCInstBuilder(AArch64::ADRP)
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.addReg(AArch64::X16)
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.addExpr(AArch64MCExpr::create(
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HwasanTagMismatchRef,
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AArch64MCExpr::VariantKind::VK_GOT_PAGE, OutContext)),
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HwasanTagMismatchRef, AArch64MCExpr::VariantKind::VK_GOT_PAGE,
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OutContext)),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::LDRXui)
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.addReg(AArch64::X16)
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.addReg(AArch64::X16)
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.addExpr(AArch64MCExpr::create(
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HwasanTagMismatchRef,
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AArch64MCExpr::VariantKind::VK_GOT_LO12, OutContext)),
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HwasanTagMismatchRef, AArch64MCExpr::VariantKind::VK_GOT_LO12,
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OutContext)),
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*STI);
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OutStreamer->EmitInstruction(
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MCInstBuilder(AArch64::BR).addReg(AArch64::X16), *STI);
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@ -1096,6 +1111,7 @@ void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
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return;
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case AArch64::HWASAN_CHECK_MEMACCESS:
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case AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:
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LowerHWASAN_CHECK_MEMACCESS(*MI);
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return;
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@ -800,6 +800,10 @@ def HWASAN_CHECK_MEMACCESS : Pseudo<
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(outs), (ins GPR64noip:$ptr, i32imm:$accessinfo),
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[(int_hwasan_check_memaccess X9, GPR64noip:$ptr, (i32 timm:$accessinfo))]>,
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Sched<[]>;
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def HWASAN_CHECK_MEMACCESS_SHORTGRANULES : Pseudo<
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(outs), (ins GPR64noip:$ptr, i32imm:$accessinfo),
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[(int_hwasan_check_memaccess_shortgranules X9, GPR64noip:$ptr, (i32 timm:$accessinfo))]>,
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Sched<[]>;
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}
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// The cycle counter PMC register is PMCCNTR_EL0.
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@ -166,6 +166,11 @@ static cl::opt<bool>
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cl::desc("instrument landing pads"), cl::Hidden,
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cl::init(false), cl::ZeroOrMore);
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static cl::opt<bool> ClUseShortGranules(
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"hwasan-use-short-granules",
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cl::desc("use short granules in allocas and outlined checks"), cl::Hidden,
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cl::init(false), cl::ZeroOrMore);
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static cl::opt<bool> ClInstrumentPersonalityFunctions(
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"hwasan-instrument-personality-functions",
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cl::desc("instrument personality functions"), cl::Hidden, cl::init(false),
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@ -269,6 +274,7 @@ private:
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bool CompileKernel;
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bool Recover;
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bool UseShortGranules;
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bool InstrumentLandingPads;
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Function *HwasanCtorFunction;
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@ -372,11 +378,14 @@ void HWAddressSanitizer::initializeModule() {
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HwasanCtorFunction = nullptr;
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// Older versions of Android do not have the required runtime support for
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// global or personality function instrumentation. On other platforms we
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// currently require using the latest version of the runtime.
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// short granules, global or personality function instrumentation. On other
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// platforms we currently require using the latest version of the runtime.
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bool NewRuntime =
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!TargetTriple.isAndroid() || !TargetTriple.isAndroidVersionLT(30);
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UseShortGranules =
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ClUseShortGranules.getNumOccurrences() ? ClUseShortGranules : NewRuntime;
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// If we don't have personality function support, fall back to landing pads.
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InstrumentLandingPads = ClInstrumentLandingPads.getNumOccurrences()
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? ClInstrumentLandingPads
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@ -608,9 +617,11 @@ void HWAddressSanitizer::instrumentMemAccessInline(Value *Ptr, bool IsWrite,
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TargetTriple.isOSBinFormatELF() && !Recover) {
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Module *M = IRB.GetInsertBlock()->getParent()->getParent();
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Ptr = IRB.CreateBitCast(Ptr, Int8PtrTy);
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IRB.CreateCall(
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Intrinsic::getDeclaration(M, Intrinsic::hwasan_check_memaccess),
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{shadowBase(), Ptr, ConstantInt::get(Int32Ty, AccessInfo)});
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IRB.CreateCall(Intrinsic::getDeclaration(
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M, UseShortGranules
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? Intrinsic::hwasan_check_memaccess_shortgranules
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: Intrinsic::hwasan_check_memaccess),
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{shadowBase(), Ptr, ConstantInt::get(Int32Ty, AccessInfo)});
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return;
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}
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@ -763,6 +774,8 @@ static uint64_t getAllocaSizeInBytes(const AllocaInst &AI) {
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bool HWAddressSanitizer::tagAlloca(IRBuilder<> &IRB, AllocaInst *AI,
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Value *Tag, size_t Size) {
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size_t AlignedSize = alignTo(Size, Mapping.getObjectAlignment());
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if (!UseShortGranules)
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Size = AlignedSize;
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Value *JustTag = IRB.CreateTrunc(Tag, IRB.getInt8Ty());
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if (ClInstrumentWithCalls) {
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@ -8,11 +8,11 @@ define i8* @f1(i8* %x0, i8* %x1) {
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: mov x9, x0
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; CHECK-NEXT: bl __hwasan_check_x1_123
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; CHECK-NEXT: bl __hwasan_check_x1_1
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; CHECK-NEXT: mov x0, x1
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; CHECK-NEXT: ldr x30, [sp], #16
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; CHECK-NEXT: ret
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call void @llvm.hwasan.check.memaccess(i8* %x0, i8* %x1, i32 123)
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call void @llvm.hwasan.check.memaccess(i8* %x0, i8* %x1, i32 1)
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ret i8* %x1
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}
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@ -22,20 +22,21 @@ define i8* @f2(i8* %x0, i8* %x1) {
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: mov x9, x1
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; CHECK-NEXT: bl __hwasan_check_x0_456
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; CHECK-NEXT: bl __hwasan_check_x0_2_short
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; CHECK-NEXT: ldr x30, [sp], #16
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; CHECK-NEXT: ret
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call void @llvm.hwasan.check.memaccess(i8* %x1, i8* %x0, i32 456)
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call void @llvm.hwasan.check.memaccess.shortgranules(i8* %x1, i8* %x0, i32 2)
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ret i8* %x0
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}
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declare void @llvm.hwasan.check.memaccess(i8*, i8*, i32)
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declare void @llvm.hwasan.check.memaccess.shortgranules(i8*, i8*, i32)
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; CHECK: .section .text.hot,"axG",@progbits,__hwasan_check_x0_456,comdat
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; CHECK-NEXT: .type __hwasan_check_x0_456,@function
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; CHECK-NEXT: .weak __hwasan_check_x0_456
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; CHECK-NEXT: .hidden __hwasan_check_x0_456
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; CHECK-NEXT: __hwasan_check_x0_456:
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; CHECK: .section .text.hot,"axG",@progbits,__hwasan_check_x0_2_short,comdat
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; CHECK-NEXT: .type __hwasan_check_x0_2_short,@function
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; CHECK-NEXT: .weak __hwasan_check_x0_2_short
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; CHECK-NEXT: .hidden __hwasan_check_x0_2_short
|
||||
; CHECK-NEXT: __hwasan_check_x0_2_short:
|
||||
; CHECK-NEXT: ubfx x16, x0, #4, #52
|
||||
; CHECK-NEXT: ldrb w16, [x9, x16]
|
||||
; CHECK-NEXT: cmp x16, x0, lsr #56
|
||||
@ -46,7 +47,7 @@ declare void @llvm.hwasan.check.memaccess(i8*, i8*, i32)
|
||||
; CHECK-NEXT: cmp w16, #15
|
||||
; CHECK-NEXT: b.hi .Ltmp2
|
||||
; CHECK-NEXT: and x17, x0, #0xf
|
||||
; CHECK-NEXT: add x17, x17, #255
|
||||
; CHECK-NEXT: add x17, x17, #3
|
||||
; CHECK-NEXT: cmp w16, w17
|
||||
; CHECK-NEXT: b.ls .Ltmp2
|
||||
; CHECK-NEXT: orr x16, x0, #0xf
|
||||
@ -56,17 +57,17 @@ declare void @llvm.hwasan.check.memaccess(i8*, i8*, i32)
|
||||
; CHECK-NEXT: .Ltmp2:
|
||||
; CHECK-NEXT: stp x0, x1, [sp, #-256]!
|
||||
; CHECK-NEXT: stp x29, x30, [sp, #232]
|
||||
; CHECK-NEXT: mov x1, #456
|
||||
; CHECK-NEXT: adrp x16, :got:__hwasan_tag_mismatch
|
||||
; CHECK-NEXT: ldr x16, [x16, :got_lo12:__hwasan_tag_mismatch]
|
||||
; CHECK-NEXT: mov x1, #2
|
||||
; CHECK-NEXT: adrp x16, :got:__hwasan_tag_mismatch_v2
|
||||
; CHECK-NEXT: ldr x16, [x16, :got_lo12:__hwasan_tag_mismatch_v2]
|
||||
; CHECK-NEXT: br x16
|
||||
|
||||
|
||||
; CHECK: .section .text.hot,"axG",@progbits,__hwasan_check_x1_123,comdat
|
||||
; CHECK-NEXT: .type __hwasan_check_x1_123,@function
|
||||
; CHECK-NEXT: .weak __hwasan_check_x1_123
|
||||
; CHECK-NEXT: .hidden __hwasan_check_x1_123
|
||||
; CHECK-NEXT: __hwasan_check_x1_123:
|
||||
; CHECK: .section .text.hot,"axG",@progbits,__hwasan_check_x1_1,comdat
|
||||
; CHECK-NEXT: .type __hwasan_check_x1_1,@function
|
||||
; CHECK-NEXT: .weak __hwasan_check_x1_1
|
||||
; CHECK-NEXT: .hidden __hwasan_check_x1_1
|
||||
; CHECK-NEXT: __hwasan_check_x1_1:
|
||||
; CHECK-NEXT: ubfx x16, x1, #4, #52
|
||||
; CHECK-NEXT: ldrb w16, [x9, x16]
|
||||
; CHECK-NEXT: cmp x16, x1, lsr #56
|
||||
@ -74,21 +75,10 @@ declare void @llvm.hwasan.check.memaccess(i8*, i8*, i32)
|
||||
; CHECK-NEXT: .Ltmp4:
|
||||
; CHECK-NEXT: ret
|
||||
; CHECK-NEXT: .Ltmp3:
|
||||
; CHECK-NEXT: cmp w16, #15
|
||||
; CHECK-NEXT: b.hi .Ltmp5
|
||||
; CHECK-NEXT: and x17, x1, #0xf
|
||||
; CHECK-NEXT: add x17, x17, #2047
|
||||
; CHECK-NEXT: cmp w16, w17
|
||||
; CHECK-NEXT: b.ls .Ltmp5
|
||||
; CHECK-NEXT: orr x16, x1, #0xf
|
||||
; CHECK-NEXT: ldrb w16, [x16]
|
||||
; CHECK-NEXT: cmp x16, x1, lsr #56
|
||||
; CHECK-NEXT: b.eq .Ltmp4
|
||||
; CHECK-NEXT: .Ltmp5:
|
||||
; CHECK-NEXT: stp x0, x1, [sp, #-256]!
|
||||
; CHECK-NEXT: stp x29, x30, [sp, #232]
|
||||
; CHECK-NEXT: mov x0, x1
|
||||
; CHECK-NEXT: mov x1, #123
|
||||
; CHECK-NEXT: mov x1, #1
|
||||
; CHECK-NEXT: adrp x16, :got:__hwasan_tag_mismatch
|
||||
; CHECK-NEXT: ldr x16, [x16, :got_lo12:__hwasan_tag_mismatch]
|
||||
; CHECK-NEXT: br x16
|
||||
|
||||
17
test/Instrumentation/HWAddressSanitizer/alloca-compat.ll
Normal file
17
test/Instrumentation/HWAddressSanitizer/alloca-compat.ll
Normal file
@ -0,0 +1,17 @@
|
||||
; Test that alloca instrumentation with old API levels does not use short granules.
|
||||
;
|
||||
; RUN: opt < %s -hwasan -S | FileCheck %s
|
||||
|
||||
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
|
||||
target triple = "aarch64--linux-android"
|
||||
|
||||
declare void @use32(i32*)
|
||||
|
||||
define void @test_alloca() sanitize_hwaddress {
|
||||
; CHECK-LABEL: @test_alloca(
|
||||
; CHECK: %[[X_TAG:[^ ]*]] = trunc i64 {{.*}} to i8
|
||||
; CHECK: call void @llvm.memset.p0i8.i64(i8* align 1 {{.*}}, i8 %[[X_TAG]], i64 1, i1 false)
|
||||
%x = alloca i32, align 4
|
||||
call void @use32(i32* nonnull %x)
|
||||
ret void
|
||||
}
|
||||
@ -5,7 +5,7 @@
|
||||
; RUN: opt < %s -hwasan -hwasan-with-ifunc=1 -hwasan-uar-retag-to-zero=0 -S | FileCheck %s --check-prefixes=CHECK,DYNAMIC-SHADOW,UAR-TAGS
|
||||
|
||||
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
|
||||
target triple = "aarch64--linux-android"
|
||||
target triple = "aarch64--linux-android10000"
|
||||
|
||||
declare void @use32(i32*)
|
||||
|
||||
|
||||
13
test/Instrumentation/HWAddressSanitizer/basic-compat.ll
Normal file
13
test/Instrumentation/HWAddressSanitizer/basic-compat.ll
Normal file
@ -0,0 +1,13 @@
|
||||
; Test that the old outlined check is used with old API levels.
|
||||
|
||||
; RUN: opt < %s -hwasan -S | FileCheck %s
|
||||
|
||||
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
|
||||
target triple = "aarch64--linux-android"
|
||||
|
||||
define i8 @test_load8(i8* %a) sanitize_hwaddress {
|
||||
; CHECK-LABEL: @test_load8(
|
||||
; CHECK: call void @llvm.hwasan.check.memaccess(i8* {{.*}}, i8* {{.*}}, i32 0)
|
||||
%b = load i8, i8* %a, align 4
|
||||
ret i8 %b
|
||||
}
|
||||
@ -14,7 +14,7 @@
|
||||
; CHECK: @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 0, void ()* @hwasan.module_ctor, i8* bitcast (void ()* @hwasan.module_ctor to i8*) }]
|
||||
|
||||
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
|
||||
target triple = "aarch64--linux-android"
|
||||
target triple = "aarch64--linux-android10000"
|
||||
|
||||
define i8 @test_load8(i8* %a) sanitize_hwaddress {
|
||||
; CHECK-LABEL: @test_load8(
|
||||
@ -56,8 +56,8 @@ define i8 @test_load8(i8* %a) sanitize_hwaddress {
|
||||
|
||||
; RECOVER: [[CONT]]:
|
||||
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess(i8* %.hwasan.shadow, i8* %a, i32 0)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess(i8* null, i8* %a, i32 0)
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %a, i32 0)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* null, i8* %a, i32 0)
|
||||
|
||||
; CHECK: %[[G:[^ ]*]] = load i8, i8* %a, align 4
|
||||
; CHECK: ret i8 %[[G]]
|
||||
@ -108,8 +108,8 @@ define i16 @test_load16(i16* %a) sanitize_hwaddress {
|
||||
; RECOVER: [[CONT]]:
|
||||
|
||||
; ABORT: %[[A:[^ ]*]] = bitcast i16* %a to i8*
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess(i8* %.hwasan.shadow, i8* %[[A]], i32 1)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess(i8* null, i8* %[[A]], i32 1)
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %[[A]], i32 1)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* null, i8* %[[A]], i32 1)
|
||||
|
||||
; CHECK: %[[G:[^ ]*]] = load i16, i16* %a, align 4
|
||||
; CHECK: ret i16 %[[G]]
|
||||
@ -136,8 +136,8 @@ define i32 @test_load32(i32* %a) sanitize_hwaddress {
|
||||
; RECOVER: br label
|
||||
|
||||
; ABORT: %[[A:[^ ]*]] = bitcast i32* %a to i8*
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess(i8* %.hwasan.shadow, i8* %[[A]], i32 2)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess(i8* null, i8* %[[A]], i32 2)
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %[[A]], i32 2)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* null, i8* %[[A]], i32 2)
|
||||
|
||||
; CHECK: %[[G:[^ ]*]] = load i32, i32* %a, align 4
|
||||
; CHECK: ret i32 %[[G]]
|
||||
@ -164,8 +164,8 @@ define i64 @test_load64(i64* %a) sanitize_hwaddress {
|
||||
; RECOVER: br label
|
||||
|
||||
; ABORT: %[[A:[^ ]*]] = bitcast i64* %a to i8*
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess(i8* %.hwasan.shadow, i8* %[[A]], i32 3)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess(i8* null, i8* %[[A]], i32 3)
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %[[A]], i32 3)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* null, i8* %[[A]], i32 3)
|
||||
|
||||
; CHECK: %[[G:[^ ]*]] = load i64, i64* %a, align 8
|
||||
; CHECK: ret i64 %[[G]]
|
||||
@ -192,8 +192,8 @@ define i128 @test_load128(i128* %a) sanitize_hwaddress {
|
||||
; RECOVER: br label
|
||||
|
||||
; ABORT: %[[A:[^ ]*]] = bitcast i128* %a to i8*
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess(i8* %.hwasan.shadow, i8* %[[A]], i32 4)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess(i8* null, i8* %[[A]], i32 4)
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %[[A]], i32 4)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* null, i8* %[[A]], i32 4)
|
||||
|
||||
; CHECK: %[[G:[^ ]*]] = load i128, i128* %a, align 16
|
||||
; CHECK: ret i128 %[[G]]
|
||||
@ -232,8 +232,8 @@ define void @test_store8(i8* %a, i8 %b) sanitize_hwaddress {
|
||||
; RECOVER: call void asm sideeffect "brk #2352", "{x0}"(i64 %[[A]])
|
||||
; RECOVER: br label
|
||||
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess(i8* %.hwasan.shadow, i8* %a, i32 16)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess(i8* null, i8* %a, i32 16)
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %a, i32 16)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* null, i8* %a, i32 16)
|
||||
|
||||
; CHECK: store i8 %b, i8* %a, align 4
|
||||
; CHECK: ret void
|
||||
@ -260,8 +260,8 @@ define void @test_store16(i16* %a, i16 %b) sanitize_hwaddress {
|
||||
; RECOVER: br label
|
||||
|
||||
; ABORT: %[[A:[^ ]*]] = bitcast i16* %a to i8*
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess(i8* %.hwasan.shadow, i8* %[[A]], i32 17)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess(i8* null, i8* %[[A]], i32 17)
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %[[A]], i32 17)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* null, i8* %[[A]], i32 17)
|
||||
|
||||
; CHECK: store i16 %b, i16* %a, align 4
|
||||
; CHECK: ret void
|
||||
@ -288,8 +288,8 @@ define void @test_store32(i32* %a, i32 %b) sanitize_hwaddress {
|
||||
; RECOVER: br label
|
||||
|
||||
; ABORT: %[[A:[^ ]*]] = bitcast i32* %a to i8*
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess(i8* %.hwasan.shadow, i8* %[[A]], i32 18)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess(i8* null, i8* %[[A]], i32 18)
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %[[A]], i32 18)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* null, i8* %[[A]], i32 18)
|
||||
|
||||
; CHECK: store i32 %b, i32* %a, align 4
|
||||
; CHECK: ret void
|
||||
@ -316,8 +316,8 @@ define void @test_store64(i64* %a, i64 %b) sanitize_hwaddress {
|
||||
; RECOVER: br label
|
||||
|
||||
; ABORT: %[[A:[^ ]*]] = bitcast i64* %a to i8*
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess(i8* %.hwasan.shadow, i8* %[[A]], i32 19)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess(i8* null, i8* %[[A]], i32 19)
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %[[A]], i32 19)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* null, i8* %[[A]], i32 19)
|
||||
|
||||
; CHECK: store i64 %b, i64* %a, align 8
|
||||
; CHECK: ret void
|
||||
@ -344,8 +344,8 @@ define void @test_store128(i128* %a, i128 %b) sanitize_hwaddress {
|
||||
; RECOVER: br label
|
||||
|
||||
; ABORT: %[[A:[^ ]*]] = bitcast i128* %a to i8*
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess(i8* %.hwasan.shadow, i8* %[[A]], i32 20)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess(i8* null, i8* %[[A]], i32 20)
|
||||
; ABORT-DYNAMIC-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* %.hwasan.shadow, i8* %[[A]], i32 20)
|
||||
; ABORT-ZERO-BASED-SHADOW: call void @llvm.hwasan.check.memaccess.shortgranules(i8* null, i8* %[[A]], i32 20)
|
||||
|
||||
; CHECK: store i128 %b, i128* %a, align 16
|
||||
; CHECK: ret void
|
||||
|
||||
Loading…
Reference in New Issue
Block a user