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Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values.
llvm-svn: 103234
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3e5720a898
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@ -782,11 +782,14 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
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AddDefaultPred(MIB.addMemOperand(MMO));
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AddDefaultPred(MIB.addMemOperand(MMO));
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} else {
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} else {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQ))
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MachineInstrBuilder MIB =
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.addReg(SrcReg, getKillRegState(isKill))
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMD))
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.addFrameIndex(FI)
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.addFrameIndex(FI)
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.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
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.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
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.addMemOperand(MMO));
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.addMemOperand(MMO);
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MIB = AddDReg(MIB, SrcReg, ARM::DSUBREG_0, getKillRegState(isKill), TRI);
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AddDReg(MIB, SrcReg, ARM::DSUBREG_1, 0, TRI);
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}
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}
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} else {
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} else {
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assert((RC == ARM::QQPRRegisterClass ||
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assert((RC == ARM::QQPRRegisterClass ||
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@ -838,10 +841,13 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
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AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO));
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AddDefaultPred(MIB.addFrameIndex(FI).addImm(128).addMemOperand(MMO));
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} else {
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} else {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQ), DestReg)
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MachineInstrBuilder MIB =
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.addFrameIndex(FI)
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMD))
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.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4))
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.addFrameIndex(FI)
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.addMemOperand(MMO));
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.addImm(ARM_AM::getAM5Opc(ARM_AM::ia, 4)))
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.addMemOperand(MMO);
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MIB = AddDReg(MIB, DestReg, ARM::DSUBREG_0, RegState::Define, TRI);
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AddDReg(MIB, DestReg, ARM::DSUBREG_1, RegState::Define, TRI);
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}
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}
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} else {
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} else {
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assert((RC == ARM::QQPRRegisterClass ||
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assert((RC == ARM::QQPRRegisterClass ||
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