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[asan-asm-instrumentation] Fixed memory references which includes %rsp as a base or an index register.
Summary: [asan-asm-instrumentation] Fixed memory references which includes %rsp as a base or an index register. Reviewers: eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5599 llvm-svn: 219602
This commit is contained in:
Yuri Gorshenin
parent
bdabb1a1e6
commit
85aae05168
@ -26,6 +26,7 @@
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#include "llvm/MC/MCTargetAsmParser.h"
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#include "llvm/MC/MCTargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include <algorithm>
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namespace llvm {
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namespace {
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@ -35,10 +36,21 @@ static cl::opt<bool> ClAsanInstrumentAssembly(
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cl::desc("instrument assembly with AddressSanitizer checks"), cl::Hidden,
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cl::init(false));
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bool IsStackReg(unsigned Reg) {
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return Reg == X86::RSP || Reg == X86::ESP || Reg == X86::SP;
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const int64_t MinAllowedDisplacement = std::numeric_limits<int32_t>::min();
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const int64_t MaxAllowedDisplacement = std::numeric_limits<int32_t>::max();
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int64_t ApplyBounds(int64_t Displacement) {
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return std::max(std::min(MaxAllowedDisplacement, Displacement),
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MinAllowedDisplacement);
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}
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bool InBounds(int64_t Displacement) {
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return Displacement >= MinAllowedDisplacement &&
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Displacement <= MaxAllowedDisplacement;
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}
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bool IsStackReg(unsigned Reg) { return Reg == X86::RSP || Reg == X86::ESP; }
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bool IsSmallMemAccess(unsigned AccessSize) { return AccessSize < 8; }
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std::string FuncName(unsigned AccessSize, bool IsWrite) {
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@ -72,7 +84,8 @@ public:
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};
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X86AddressSanitizer(const MCSubtargetInfo &STI)
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: X86AsmInstrumentation(STI), RepPrefix(false) {}
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: X86AsmInstrumentation(STI), RepPrefix(false), OrigSPOffset(0) {}
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virtual ~X86AddressSanitizer() {}
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// X86AsmInstrumentation implementation:
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@ -92,11 +105,6 @@ public:
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EmitInstruction(Out, Inst);
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}
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// Should be implemented differently in x86_32 and x86_64 subclasses.
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virtual void StoreFlags(MCStreamer &Out) = 0;
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virtual void RestoreFlags(MCStreamer &Out) = 0;
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// Adjusts up stack and saves all registers used in instrumentation.
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virtual void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
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MCContext &Ctx,
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@ -133,8 +141,31 @@ public:
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protected:
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void EmitLabel(MCStreamer &Out, MCSymbol *Label) { Out.EmitLabel(Label); }
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void EmitLEA(X86Operand &Op, MVT::SimpleValueType VT, unsigned Reg,
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MCStreamer &Out) {
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assert(VT == MVT::i32 || VT == MVT::i64);
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MCInst Inst;
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Inst.setOpcode(VT == MVT::i32 ? X86::LEA32r : X86::LEA64r);
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Inst.addOperand(MCOperand::CreateReg(getX86SubSuperRegister(Reg, VT)));
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Op.addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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void ComputeMemOperandAddress(X86Operand &Op, MVT::SimpleValueType VT,
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unsigned Reg, MCContext &Ctx, MCStreamer &Out);
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// Creates new memory operand with Displacement added to an original
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// displacement. Residue will contain a residue which could happen when the
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// total displacement exceeds 32-bit limitation.
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std::unique_ptr<X86Operand> AddDisplacement(X86Operand &Op,
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int64_t Displacement,
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MCContext &Ctx, int64_t *Residue);
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// True when previous instruction was actually REP prefix.
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bool RepPrefix;
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// Offset from the original SP register.
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int64_t OrigSPOffset;
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};
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void X86AddressSanitizer::InstrumentMemOperand(
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@ -276,12 +307,6 @@ void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst,
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MCParsedAsmOperand &Op = *Operands[Ix];
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if (Op.isMem()) {
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X86Operand &MemOp = static_cast<X86Operand &>(Op);
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// FIXME: get rid of this limitation.
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if (IsStackReg(MemOp.getMemBaseReg()) ||
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IsStackReg(MemOp.getMemIndexReg())) {
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continue;
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}
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InstrumentMemOperandPrologue(RegCtx, Ctx, Out);
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InstrumentMemOperand(MemOp, AccessSize, IsWrite, RegCtx, Ctx, Out);
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InstrumentMemOperandEpilogue(RegCtx, Ctx, Out);
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@ -289,6 +314,67 @@ void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst,
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}
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}
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void X86AddressSanitizer::ComputeMemOperandAddress(X86Operand &Op,
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MVT::SimpleValueType VT,
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unsigned Reg, MCContext &Ctx,
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MCStreamer &Out) {
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int64_t Displacement = 0;
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if (IsStackReg(Op.getMemBaseReg()))
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Displacement -= OrigSPOffset;
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if (IsStackReg(Op.getMemIndexReg()))
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Displacement -= OrigSPOffset * Op.getMemScale();
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assert(Displacement >= 0);
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// Emit Op as is.
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if (Displacement == 0) {
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EmitLEA(Op, VT, Reg, Out);
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return;
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}
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int64_t Residue;
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std::unique_ptr<X86Operand> NewOp =
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AddDisplacement(Op, Displacement, Ctx, &Residue);
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EmitLEA(*NewOp, VT, Reg, Out);
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while (Residue != 0) {
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const MCConstantExpr *Disp =
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MCConstantExpr::Create(ApplyBounds(Residue), Ctx);
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std::unique_ptr<X86Operand> DispOp =
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X86Operand::CreateMem(0, Disp, Reg, 0, 1, SMLoc(), SMLoc());
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EmitLEA(*DispOp, VT, Reg, Out);
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Residue -= Disp->getValue();
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}
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}
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std::unique_ptr<X86Operand>
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X86AddressSanitizer::AddDisplacement(X86Operand &Op, int64_t Displacement,
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MCContext &Ctx, int64_t *Residue) {
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assert(Displacement >= 0);
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if (Displacement == 0 ||
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(Op.getMemDisp() && Op.getMemDisp()->getKind() != MCExpr::Constant)) {
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*Residue = Displacement;
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return X86Operand::CreateMem(Op.getMemSegReg(), Op.getMemDisp(),
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Op.getMemBaseReg(), Op.getMemIndexReg(),
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Op.getMemScale(), SMLoc(), SMLoc());
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}
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int64_t OrigDisplacement =
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static_cast<const MCConstantExpr *>(Op.getMemDisp())->getValue();
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assert(InBounds(OrigDisplacement));
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Displacement += OrigDisplacement;
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int64_t NewDisplacement = ApplyBounds(Displacement);
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assert(InBounds(NewDisplacement));
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*Residue = Displacement - NewDisplacement;
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const MCExpr *Disp = MCConstantExpr::Create(NewDisplacement, Ctx);
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return X86Operand::CreateMem(Op.getMemSegReg(), Disp, Op.getMemBaseReg(),
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Op.getMemIndexReg(), Op.getMemScale(), SMLoc(),
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SMLoc());
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}
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class X86AddressSanitizer32 : public X86AddressSanitizer {
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public:
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static const long kShadowOffset = 0x20000000;
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@ -305,12 +391,24 @@ public:
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return getX86SubSuperRegister(FrameReg, MVT::i32);
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}
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virtual void StoreFlags(MCStreamer &Out) override {
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EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
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void SpillReg(MCStreamer &Out, unsigned Reg) {
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EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(Reg));
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OrigSPOffset -= 4;
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}
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virtual void RestoreFlags(MCStreamer &Out) override {
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void RestoreReg(MCStreamer &Out, unsigned Reg) {
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EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(Reg));
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OrigSPOffset += 4;
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}
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void StoreFlags(MCStreamer &Out) {
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EmitInstruction(Out, MCInstBuilder(X86::PUSHF32));
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OrigSPOffset -= 4;
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}
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void RestoreFlags(MCStreamer &Out) {
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EmitInstruction(Out, MCInstBuilder(X86::POPF32));
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OrigSPOffset += 4;
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}
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virtual void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
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@ -319,28 +417,21 @@ public:
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const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
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unsigned FrameReg = GetFrameReg(Ctx, Out);
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if (MRI && FrameReg != X86::NoRegister) {
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EmitInstruction(
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Out, MCInstBuilder(X86::PUSH32r).addReg(X86::EBP));
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SpillReg(Out, X86::EBP);
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if (FrameReg == X86::ESP) {
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Out.EmitCFIAdjustCfaOffset(4 /* byte size of the FrameReg */);
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Out.EmitCFIRelOffset(
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MRI->getDwarfRegNum(X86::EBP, true /* IsEH */), 0);
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Out.EmitCFIRelOffset(MRI->getDwarfRegNum(X86::EBP, true /* IsEH */), 0);
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}
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV32rr).addReg(X86::EBP).addReg(FrameReg));
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Out.EmitCFIRememberState();
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Out.EmitCFIDefCfaRegister(
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MRI->getDwarfRegNum(X86::EBP, true /* IsEH */));
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Out.EmitCFIDefCfaRegister(MRI->getDwarfRegNum(X86::EBP, true /* IsEH */));
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}
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EmitInstruction(
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Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.addressReg(MVT::i32)));
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EmitInstruction(
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Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.shadowReg(MVT::i32)));
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if (RegCtx.ScratchReg != X86::NoRegister) {
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EmitInstruction(
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Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.scratchReg(MVT::i32)));
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}
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SpillReg(Out, RegCtx.addressReg(MVT::i32));
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SpillReg(Out, RegCtx.shadowReg(MVT::i32));
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if (RegCtx.ScratchReg != X86::NoRegister)
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SpillReg(Out, RegCtx.scratchReg(MVT::i32));
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StoreFlags(Out);
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}
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@ -348,19 +439,14 @@ public:
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MCContext &Ctx,
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MCStreamer &Out) override {
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RestoreFlags(Out);
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if (RegCtx.ScratchReg != X86::NoRegister) {
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EmitInstruction(
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Out, MCInstBuilder(X86::POP32r).addReg(RegCtx.scratchReg(MVT::i32)));
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}
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EmitInstruction(
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Out, MCInstBuilder(X86::POP32r).addReg(RegCtx.shadowReg(MVT::i32)));
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EmitInstruction(
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Out, MCInstBuilder(X86::POP32r).addReg(RegCtx.addressReg(MVT::i32)));
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if (RegCtx.ScratchReg != X86::NoRegister)
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RestoreReg(Out, RegCtx.scratchReg(MVT::i32));
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RestoreReg(Out, RegCtx.shadowReg(MVT::i32));
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RestoreReg(Out, RegCtx.addressReg(MVT::i32));
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unsigned FrameReg = GetFrameReg(Ctx, Out);
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if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
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EmitInstruction(
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Out, MCInstBuilder(X86::POP32r).addReg(X86::EBP));
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RestoreReg(Out, X86::EBP);
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Out.EmitCFIRestoreState();
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if (FrameReg == X86::ESP)
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Out.EmitCFIAdjustCfaOffset(-4 /* byte size of the FrameReg */);
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@ -411,13 +497,7 @@ void X86AddressSanitizer32::InstrumentMemOperandSmall(
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assert(RegCtx.ScratchReg != X86::NoRegister);
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unsigned ScratchRegI32 = RegCtx.scratchReg(MVT::i32);
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{
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MCInst Inst;
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Inst.setOpcode(X86::LEA32r);
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Inst.addOperand(MCOperand::CreateReg(AddressRegI32));
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Op.addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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ComputeMemOperandAddress(Op, MVT::i32, AddressRegI32, Ctx, Out);
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EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
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AddressRegI32));
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@ -454,15 +534,10 @@ void X86AddressSanitizer32::InstrumentMemOperandSmall(
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case 1:
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break;
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case 2: {
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MCInst Inst;
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Inst.setOpcode(X86::LEA32r);
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Inst.addOperand(MCOperand::CreateReg(ScratchRegI32));
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const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(0, Disp, ScratchRegI32, 0, 1, SMLoc(), SMLoc()));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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EmitLEA(*Op, MVT::i32, ScratchRegI32, Out);
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break;
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}
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case 4:
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@ -493,13 +568,7 @@ void X86AddressSanitizer32::InstrumentMemOperandLarge(
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unsigned AddressRegI32 = RegCtx.addressReg(MVT::i32);
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unsigned ShadowRegI32 = RegCtx.shadowReg(MVT::i32);
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{
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MCInst Inst;
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Inst.setOpcode(X86::LEA32r);
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Inst.addOperand(MCOperand::CreateReg(AddressRegI32));
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Op.addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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}
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ComputeMemOperandAddress(Op, MVT::i32, AddressRegI32, Ctx, Out);
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EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg(
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AddressRegI32));
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@ -571,12 +640,24 @@ public:
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return getX86SubSuperRegister(FrameReg, MVT::i64);
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}
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virtual void StoreFlags(MCStreamer &Out) override {
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EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
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void SpillReg(MCStreamer &Out, unsigned Reg) {
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EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(Reg));
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OrigSPOffset -= 8;
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}
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virtual void RestoreFlags(MCStreamer &Out) override {
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void RestoreReg(MCStreamer &Out, unsigned Reg) {
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EmitInstruction(Out, MCInstBuilder(X86::POP64r).addReg(Reg));
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OrigSPOffset += 8;
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}
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void StoreFlags(MCStreamer &Out) {
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EmitInstruction(Out, MCInstBuilder(X86::PUSHF64));
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OrigSPOffset -= 8;
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}
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void RestoreFlags(MCStreamer &Out) {
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EmitInstruction(Out, MCInstBuilder(X86::POPF64));
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OrigSPOffset += 8;
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}
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virtual void InstrumentMemOperandPrologue(const RegisterContext &RegCtx,
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@ -585,28 +666,22 @@ public:
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const MCRegisterInfo *MRI = Ctx.getRegisterInfo();
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unsigned FrameReg = GetFrameReg(Ctx, Out);
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if (MRI && FrameReg != X86::NoRegister) {
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EmitInstruction(Out, MCInstBuilder(X86::PUSH64r).addReg(X86::RBP));
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SpillReg(Out, X86::RBP);
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if (FrameReg == X86::RSP) {
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Out.EmitCFIAdjustCfaOffset(8 /* byte size of the FrameReg */);
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Out.EmitCFIRelOffset(
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MRI->getDwarfRegNum(X86::RBP, true /* IsEH */), 0);
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Out.EmitCFIRelOffset(MRI->getDwarfRegNum(X86::RBP, true /* IsEH */), 0);
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}
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EmitInstruction(
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Out, MCInstBuilder(X86::MOV64rr).addReg(X86::RBP).addReg(FrameReg));
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Out.EmitCFIRememberState();
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Out.EmitCFIDefCfaRegister(
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MRI->getDwarfRegNum(X86::RBP, true /* IsEH */));
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Out.EmitCFIDefCfaRegister(MRI->getDwarfRegNum(X86::RBP, true /* IsEH */));
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}
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EmitAdjustRSP(Ctx, Out, -128);
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EmitInstruction(
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Out, MCInstBuilder(X86::PUSH64r).addReg(RegCtx.shadowReg(MVT::i64)));
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EmitInstruction(
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Out, MCInstBuilder(X86::PUSH64r).addReg(RegCtx.addressReg(MVT::i64)));
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if (RegCtx.ScratchReg != X86::NoRegister) {
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EmitInstruction(
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Out, MCInstBuilder(X86::PUSH64r).addReg(RegCtx.scratchReg(MVT::i64)));
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}
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SpillReg(Out, RegCtx.shadowReg(MVT::i64));
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SpillReg(Out, RegCtx.addressReg(MVT::i64));
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if (RegCtx.ScratchReg != X86::NoRegister)
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SpillReg(Out, RegCtx.scratchReg(MVT::i64));
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StoreFlags(Out);
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}
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@ -614,20 +689,15 @@ public:
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MCContext &Ctx,
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MCStreamer &Out) override {
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RestoreFlags(Out);
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if (RegCtx.ScratchReg != X86::NoRegister) {
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EmitInstruction(
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Out, MCInstBuilder(X86::POP64r).addReg(RegCtx.scratchReg(MVT::i64)));
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}
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EmitInstruction(
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Out, MCInstBuilder(X86::POP64r).addReg(RegCtx.addressReg(MVT::i64)));
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EmitInstruction(
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Out, MCInstBuilder(X86::POP64r).addReg(RegCtx.shadowReg(MVT::i64)));
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if (RegCtx.ScratchReg != X86::NoRegister)
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RestoreReg(Out, RegCtx.scratchReg(MVT::i64));
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RestoreReg(Out, RegCtx.addressReg(MVT::i64));
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RestoreReg(Out, RegCtx.shadowReg(MVT::i64));
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EmitAdjustRSP(Ctx, Out, 128);
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unsigned FrameReg = GetFrameReg(Ctx, Out);
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if (Ctx.getRegisterInfo() && FrameReg != X86::NoRegister) {
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EmitInstruction(
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Out, MCInstBuilder(X86::POP64r).addReg(X86::RBP));
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RestoreReg(Out, X86::RBP);
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Out.EmitCFIRestoreState();
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if (FrameReg == X86::RSP)
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Out.EmitCFIAdjustCfaOffset(-8 /* byte size of the FrameReg */);
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@ -649,15 +719,11 @@ public:
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private:
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void EmitAdjustRSP(MCContext &Ctx, MCStreamer &Out, long Offset) {
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MCInst Inst;
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Inst.setOpcode(X86::LEA64r);
|
||||
Inst.addOperand(MCOperand::CreateReg(X86::RSP));
|
||||
|
||||
const MCExpr *Disp = MCConstantExpr::Create(Offset, Ctx);
|
||||
std::unique_ptr<X86Operand> Op(
|
||||
X86Operand::CreateMem(0, Disp, X86::RSP, 0, 1, SMLoc(), SMLoc()));
|
||||
Op->addMemOperands(Inst, 5);
|
||||
EmitInstruction(Out, Inst);
|
||||
EmitLEA(*Op, MVT::i64, X86::RSP, Out);
|
||||
OrigSPOffset += Offset;
|
||||
}
|
||||
|
||||
void EmitCallAsanReport(unsigned AccessSize, bool IsWrite, MCContext &Ctx,
|
||||
@ -694,13 +760,8 @@ void X86AddressSanitizer64::InstrumentMemOperandSmall(
|
||||
assert(RegCtx.ScratchReg != X86::NoRegister);
|
||||
unsigned ScratchRegI32 = RegCtx.scratchReg(MVT::i32);
|
||||
|
||||
{
|
||||
MCInst Inst;
|
||||
Inst.setOpcode(X86::LEA64r);
|
||||
Inst.addOperand(MCOperand::CreateReg(AddressRegI64));
|
||||
Op.addMemOperands(Inst, 5);
|
||||
EmitInstruction(Out, Inst);
|
||||
}
|
||||
ComputeMemOperandAddress(Op, MVT::i64, AddressRegI64, Ctx, Out);
|
||||
|
||||
EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(ShadowRegI64).addReg(
|
||||
AddressRegI64));
|
||||
EmitInstruction(Out, MCInstBuilder(X86::SHR64ri)
|
||||
@ -735,15 +796,10 @@ void X86AddressSanitizer64::InstrumentMemOperandSmall(
|
||||
case 1:
|
||||
break;
|
||||
case 2: {
|
||||
MCInst Inst;
|
||||
Inst.setOpcode(X86::LEA32r);
|
||||
Inst.addOperand(MCOperand::CreateReg(ScratchRegI32));
|
||||
|
||||
const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
|
||||
std::unique_ptr<X86Operand> Op(
|
||||
X86Operand::CreateMem(0, Disp, ScratchRegI32, 0, 1, SMLoc(), SMLoc()));
|
||||
Op->addMemOperands(Inst, 5);
|
||||
EmitInstruction(Out, Inst);
|
||||
EmitLEA(*Op, MVT::i32, ScratchRegI32, Out);
|
||||
break;
|
||||
}
|
||||
case 4:
|
||||
@ -774,13 +830,8 @@ void X86AddressSanitizer64::InstrumentMemOperandLarge(
|
||||
unsigned AddressRegI64 = RegCtx.addressReg(MVT::i64);
|
||||
unsigned ShadowRegI64 = RegCtx.shadowReg(MVT::i64);
|
||||
|
||||
{
|
||||
MCInst Inst;
|
||||
Inst.setOpcode(X86::LEA64r);
|
||||
Inst.addOperand(MCOperand::CreateReg(AddressRegI64));
|
||||
Op.addMemOperands(Inst, 5);
|
||||
EmitInstruction(Out, Inst);
|
||||
}
|
||||
ComputeMemOperandAddress(Op, MVT::i64, AddressRegI64, Ctx, Out);
|
||||
|
||||
EmitInstruction(Out, MCInstBuilder(X86::MOV64rr).addReg(ShadowRegI64).addReg(
|
||||
AddressRegI64));
|
||||
EmitInstruction(Out, MCInstBuilder(X86::SHR64ri)
|
||||
|
||||
45
test/Instrumentation/AddressSanitizer/X86/asm_rsp_mem_op.s
Normal file
45
test/Instrumentation/AddressSanitizer/X86/asm_rsp_mem_op.s
Normal file
@ -0,0 +1,45 @@
|
||||
# The test verifies that memory references through %rsp are correctly
|
||||
# adjusted after instrumentation.
|
||||
|
||||
# RUN: llvm-mc %s -triple=x86_64-unknown-linux-gnu -asm-instrumentation=address -asan-instrument-assembly | FileCheck %s
|
||||
|
||||
# CHECK-LABEL: rsp_access
|
||||
# CHECK: leaq -128(%rsp), %rsp
|
||||
# CHECK: pushq %rax
|
||||
# CHECK: pushq %rdi
|
||||
# CHECK: pushfq
|
||||
# CHECK: leaq 160(%rsp), %rdi
|
||||
# CHECK: callq __asan_report_load8@PLT
|
||||
# CHECK: popfq
|
||||
# CHECK: popq %rdi
|
||||
# CHECK: popq %rax
|
||||
# CHECK: leaq 128(%rsp), %rsp
|
||||
# CHECK: movq 8(%rsp), %rax
|
||||
# CHECK: retq
|
||||
|
||||
.text
|
||||
.globl rsp_access
|
||||
.type rsp_access,@function
|
||||
rsp_access:
|
||||
movq 8(%rsp), %rax
|
||||
retq
|
||||
|
||||
# CHECK-LABEL: rsp_32bit_access
|
||||
# CHECK: leaq -128(%rsp), %rsp
|
||||
# CHECK: pushq %rax
|
||||
# CHECK: pushq %rdi
|
||||
# CHECK: pushfq
|
||||
# CHECK: leaq 2147483647(%rsp), %rdi
|
||||
# CHECK: leaq 145(%rdi), %rdi
|
||||
# CHECK: callq __asan_report_load8@PLT
|
||||
# CHECK: popfq
|
||||
# CHECK: popq %rdi
|
||||
# CHECK: popq %rax
|
||||
# CHECK: leaq 128(%rsp), %rsp
|
||||
# CHECK: movq 2147483640(%rsp), %rax
|
||||
# CHECK: retq
|
||||
.globl rsp_32bit_access
|
||||
.type rsp_32bit_access,@function
|
||||
rsp_32bit_access:
|
||||
movq 2147483640(%rsp), %rax
|
||||
retq
|
||||
Loading…
Reference in New Issue
Block a user