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X86: validate 'int' instruction
The int instruction takes as an operand an 8-bit immediate value. Validate that the input is valid rather than silently truncating the value. llvm-svn: 225941
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@ -684,6 +684,7 @@ private:
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bool ParseDirectiveWord(unsigned Size, SMLoc L);
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bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
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bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
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bool processInstruction(MCInst &Inst, const OperandVector &Ops);
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/// Wrapper around MCStreamer::EmitInstruction(). Possibly adds
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@ -2272,6 +2273,20 @@ static bool convert64i32to64ri8(MCInst &Inst, unsigned Opcode,
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return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
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}
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bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
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switch (Inst.getOpcode()) {
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default: return true;
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case X86::INT:
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assert(Inst.getOperand(0).isImm() && "expected immediate");
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if (Inst.getOperand(0).getImm() > 255) {
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Error(Ops[1]->getStartLoc(), "interrupt vector must be in range [0-255]");
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return false;
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}
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return true;
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}
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llvm_unreachable("handle the instruction appropriately");
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}
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bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
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switch (Inst.getOpcode()) {
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default: return false;
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@ -2434,6 +2449,9 @@ bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
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isParsingIntelSyntax())) {
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default: llvm_unreachable("Unexpected match result!");
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case Match_Success:
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if (!validateInstruction(Inst, Operands))
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return true;
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// Some instructions need post-processing to, for example, tweak which
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// encoding is selected. Loop on it while changes happen so the
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// individual transformations can chain off each other.
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@ -2677,6 +2695,9 @@ bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
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unsigned NumSuccessfulMatches =
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std::count(std::begin(Match), std::end(Match), Match_Success);
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if (NumSuccessfulMatches == 1) {
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if (!validateInstruction(Inst, Operands))
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return true;
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// Some instructions need post-processing to, for example, tweak which
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// encoding is selected. Loop on it while changes happen so the individual
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// transformations can chain off each other.
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7
test/MC/X86/validate-inst-att.s
Normal file
7
test/MC/X86/validate-inst-att.s
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@ -0,0 +1,7 @@
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# RUN: not llvm-mc -triple i686 -filetype asm -o /dev/null %s 2>&1 | FileCheck %s
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.text
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int $65535
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# CHECK: error: interrupt vector must be in range [0-255]
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# CHECK: int $65535
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# CHECK: ^
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9
test/MC/X86/validate-inst-intel.s
Normal file
9
test/MC/X86/validate-inst-intel.s
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@ -0,0 +1,9 @@
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# RUN: not llvm-mc -x86-asm-syntax intel -triple i686 -filetype asm -o /dev/null %s 2>&1 \
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# RUN: | FileCheck %s
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.text
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int 65535
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# CHECK: error: interrupt vector must be in range [0-255]
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# CHECK: int 65535
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# CHECK: ^
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