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Pre-commit test for PPC vector extraction test
This commit is contained in:
Qiu Chaofan
parent
c48d82de15
commit
85b7a12c42
@ -8,6 +8,7 @@ define zeroext i8 @test1(<16 x i8> %a, i32 signext %index) {
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; CHECK-LE-NEXT: vextubrx 3, 5, 2
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; CHECK-LE-NEXT: clrldi 3, 3, 56
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test1:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vextublx 3, 5, 2
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@ -25,6 +26,7 @@ define signext i8 @test2(<16 x i8> %a, i32 signext %index) {
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; CHECK-LE-NEXT: vextubrx 3, 5, 2
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; CHECK-LE-NEXT: extsb 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test2:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vextublx 3, 5, 2
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@ -43,6 +45,7 @@ define zeroext i16 @test3(<8 x i16> %a, i32 signext %index) {
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; CHECK-LE-NEXT: vextuhrx 3, 3, 2
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; CHECK-LE-NEXT: clrldi 3, 3, 48
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test3:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30
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@ -62,6 +65,7 @@ define signext i16 @test4(<8 x i16> %a, i32 signext %index) {
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; CHECK-LE-NEXT: vextuhrx 3, 3, 2
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; CHECK-LE-NEXT: extsh 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test4:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30
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@ -80,6 +84,7 @@ define zeroext i32 @test5(<4 x i32> %a, i32 signext %index) {
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; CHECK-LE-NEXT: rlwinm 3, 5, 2, 28, 29
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; CHECK-LE-NEXT: vextuwrx 3, 3, 2
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test5:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29
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@ -98,6 +103,7 @@ define signext i32 @test6(<4 x i32> %a, i32 signext %index) {
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; CHECK-LE-NEXT: vextuwrx 3, 3, 2
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; CHECK-LE-NEXT: extsw 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test6:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29
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@ -118,6 +124,7 @@ define zeroext i8 @test7(<16 x i8> %a) {
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; CHECK-LE-NEXT: vextubrx 3, 3, 2
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; CHECK-LE-NEXT: clrldi 3, 3, 56
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test7:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li 3, 1
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@ -137,6 +144,7 @@ define zeroext i16 @test8(<8 x i16> %a) {
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; CHECK-LE-NEXT: vextuhrx 3, 3, 2
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; CHECK-LE-NEXT: clrldi 3, 3, 48
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test8:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li 3, 2
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@ -155,6 +163,7 @@ define zeroext i32 @test9(<4 x i32> %a) {
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; CHECK-LE-NEXT: li 3, 12
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; CHECK-LE-NEXT: vextuwrx 3, 3, 2
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test9:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li 3, 12
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@ -165,3 +174,32 @@ entry:
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%vecext = extractelement <4 x i32> %a, i32 3
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ret i32 %vecext
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}
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define double @test10(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LE-LABEL: test10:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: addis 3, 2, .LCPI9_0@toc@ha
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; CHECK-LE-NEXT: addi 3, 3, .LCPI9_0@toc@l
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; CHECK-LE-NEXT: lxvx 36, 0, 3
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; CHECK-LE-NEXT: addis 3, 2, .LCPI9_1@toc@ha
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; CHECK-LE-NEXT: lfs 1, .LCPI9_1@toc@l(3)
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; CHECK-LE-NEXT: vperm 2, 2, 3, 4
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; CHECK-LE-NEXT: xxswapd 0, 34
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; CHECK-LE-NEXT: xsadddp 1, 0, 1
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test10:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addis 3, 2, .LCPI9_0@toc@ha
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; CHECK-BE-NEXT: vmrghw 3, 3, 2
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; CHECK-BE-NEXT: lfs 0, .LCPI9_0@toc@l(3)
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; CHECK-BE-NEXT: vmrglw 2, 3, 2
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; CHECK-BE-NEXT: xsadddp 1, 34, 0
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; CHECK-BE-NEXT: blr
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entry:
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%shuffle = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 5, i32 2, i32 3, i32 7>
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%cast = bitcast <4 x i32> %shuffle to <2 x double>
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%extract = extractelement <2 x double> %cast, i32 0
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%add = fadd double %extract, 1.0000
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ret double %add
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}
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@ -9,6 +9,7 @@ define zeroext i8 @test_add1(<16 x i8> %a, i32 signext %index, i8 zeroext %c) {
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; CHECK-LE-NEXT: add 3, 3, 6
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; CHECK-LE-NEXT: clrldi 3, 3, 56
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_add1:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vextublx 3, 5, 2
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@ -31,6 +32,7 @@ define signext i8 @test_add2(<16 x i8> %a, i32 signext %index, i8 signext %c) {
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; CHECK-LE-NEXT: add 3, 3, 6
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; CHECK-LE-NEXT: extsb 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_add2:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vextublx 3, 5, 2
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@ -54,6 +56,7 @@ define zeroext i16 @test_add3(<8 x i16> %a, i32 signext %index, i16 zeroext %c)
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; CHECK-LE-NEXT: add 3, 3, 6
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; CHECK-LE-NEXT: clrldi 3, 3, 48
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_add3:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30
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@ -78,6 +81,7 @@ define signext i16 @test_add4(<8 x i16> %a, i32 signext %index, i16 signext %c)
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; CHECK-LE-NEXT: add 3, 3, 6
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; CHECK-LE-NEXT: extsh 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_add4:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: rlwinm 3, 5, 1, 28, 30
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@ -102,6 +106,7 @@ define zeroext i32 @test_add5(<4 x i32> %a, i32 signext %index, i32 zeroext %c)
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; CHECK-LE-NEXT: add 3, 3, 6
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; CHECK-LE-NEXT: clrldi 3, 3, 32
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_add5:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29
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@ -123,6 +128,7 @@ define signext i32 @test_add6(<4 x i32> %a, i32 signext %index, i32 signext %c)
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; CHECK-LE-NEXT: add 3, 3, 6
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; CHECK-LE-NEXT: extsw 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test_add6:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: rlwinm 3, 5, 2, 28, 29
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@ -142,6 +148,7 @@ define zeroext i32 @test7(<4 x i32> %a) {
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: mfvsrwz 3, 34
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test7:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li 3, 8
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@ -159,6 +166,7 @@ define zeroext i32 @testadd_7(<4 x i32> %a, i32 zeroext %c) {
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; CHECK-LE-NEXT: add 3, 3, 5
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; CHECK-LE-NEXT: clrldi 3, 3, 32
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: testadd_7:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li 3, 8
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@ -178,6 +186,7 @@ define signext i32 @test8(<4 x i32> %a) {
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; CHECK-LE-NEXT: mfvsrwz 3, 34
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; CHECK-LE-NEXT: extsw 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test8:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li 3, 8
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@ -196,6 +205,7 @@ define signext i32 @testadd_8(<4 x i32> %a, i32 signext %c) {
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; CHECK-LE-NEXT: add 3, 3, 5
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; CHECK-LE-NEXT: extsw 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: testadd_8:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: li 3, 8
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@ -217,6 +227,7 @@ define signext i32 @test9(<4 x i32> %a) {
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; CHECK-LE-NEXT: vextuwrx 3, 3, 2
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; CHECK-LE-NEXT: extsw 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: test9:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: mfvsrwz 3, 34
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@ -235,6 +246,7 @@ define signext i32 @testadd_9(<4 x i32> %a, i32 signext %c) {
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; CHECK-LE-NEXT: add 3, 3, 5
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; CHECK-LE-NEXT: extsw 3, 3
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; CHECK-LE-NEXT: blr
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;
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; CHECK-BE-LABEL: testadd_9:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: mfvsrwz 3, 34
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