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[InstCombine] Fold select (icmp sgt x, -1), lshr (X, Y), ashr (X, Y) to ashr (X, Y))
Summary: (select (icmp sgt x, -1), lshr (X, Y), ashr (X, Y)) -> ashr (X, Y)) (select (icmp slt x, 1), ashr (X, Y), lshr (X, Y)) -> ashr (X, Y)) Fixes PR41173 Alive proof by @lebedev.ri (thanks) Name: PR41173 %cmp = icmp slt i32 %x, 1 %shr = lshr i32 %x, %y %shr1 = ashr i32 %x, %y %retval.0 = select i1 %cmp, i32 %shr1, i32 %shr => %retval.0 = ashr i32 %x, %y Optimization: PR41173 Done: 1 Optimization is correct! Reviewers: lebedev.ri, spatel Reviewed By: lebedev.ri Subscribers: nikic, craig.topper, llvm-commits, lebedev.ri Tags: #llvm Differential Revision: https://reviews.llvm.org/D64285 llvm-svn: 365893
This commit is contained in:
David Bolvansky
parent
257f3196b6
commit
85b7b16172
@ -531,6 +531,44 @@ static Instruction *foldSelectICmpAndAnd(Type *SelType, const ICmpInst *Cmp,
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return new ZExtInst(ICmpNeZero, SelType);
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}
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/// We want to turn:
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/// (select (icmp sgt x, C), lshr (X, Y), ashr (X, Y)); iff C s>= -1
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/// (select (icmp slt x, C), ashr (X, Y), lshr (X, Y)); iff C s>= 0
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/// into:
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/// ashr (X, Y)
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static Value *foldSelectICmpLshrAshr(const ICmpInst *IC, Value *TrueVal,
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Value *FalseVal,
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InstCombiner::BuilderTy &Builder) {
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ICmpInst::Predicate Pred = IC->getPredicate();
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Value *CmpLHS = IC->getOperand(0);
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Value *CmpRHS = IC->getOperand(1);
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Value *X, *Y;
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unsigned Bitwidth = CmpRHS->getType()->getScalarSizeInBits();
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if ((Pred != ICmpInst::ICMP_SGT ||
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!match(CmpRHS,
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m_SpecificInt_ICMP(ICmpInst::ICMP_SGE, APInt(Bitwidth, -1)))) &&
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(Pred != ICmpInst::ICMP_SLT ||
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!match(CmpRHS,
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m_SpecificInt_ICMP(ICmpInst::ICMP_SGE, APInt(Bitwidth, 0)))))
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return nullptr;
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// Canonicalize so that ashr is in FalseVal.
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if (Pred == ICmpInst::ICMP_SLT)
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std::swap(TrueVal, FalseVal);
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if (match(TrueVal, m_LShr(m_Value(X), m_Value(Y))) &&
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match(FalseVal, m_AShr(m_Specific(X), m_Specific(Y))) &&
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match(CmpLHS, m_Specific(X))) {
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const auto *Ashr = cast<Instruction>(FalseVal);
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// if lshr is not exact and ashr is, this new ashr must not be exact.
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bool IsExact = Ashr->isExact() && cast<Instruction>(TrueVal)->isExact();
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return Builder.CreateAShr(X, Y, IC->getName(), IsExact);
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}
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return nullptr;
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}
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/// We want to turn:
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/// (select (icmp eq (and X, C1), 0), Y, (or Y, C2))
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/// into:
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@ -1112,6 +1150,9 @@ Instruction *InstCombiner::foldSelectInstWithICmp(SelectInst &SI,
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if (Value *V = foldSelectICmpAndOr(ICI, TrueVal, FalseVal, Builder))
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return replaceInstUsesWith(SI, V);
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if (Value *V = foldSelectICmpLshrAshr(ICI, TrueVal, FalseVal, Builder))
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return replaceInstUsesWith(SI, V);
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if (Value *V = foldSelectCttzCtlz(ICI, TrueVal, FalseVal, Builder))
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return replaceInstUsesWith(SI, V);
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@ -3,11 +3,8 @@
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define i32 @ashr_lshr_exact_ashr_only(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_exact_ashr_only(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: ret i32 [[RET]]
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; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[CMP1]]
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;
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%cmp = icmp sgt i32 %x, -1
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%l = lshr i32 %x, %y
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@ -18,11 +15,8 @@ define i32 @ashr_lshr_exact_ashr_only(i32 %x, i32 %y) {
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define i32 @ashr_lshr_no_exact(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_no_exact(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: ret i32 [[RET]]
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; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[CMP1]]
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;
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%cmp = icmp sgt i32 %x, -1
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%l = lshr i32 %x, %y
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@ -33,11 +27,8 @@ define i32 @ashr_lshr_no_exact(i32 %x, i32 %y) {
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define i32 @ashr_lshr_exact_both(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_exact_both(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: ret i32 [[RET]]
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; CHECK-NEXT: [[CMP1:%.*]] = ashr exact i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[CMP1]]
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;
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%cmp = icmp sgt i32 %x, -1
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%l = lshr exact i32 %x, %y
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@ -48,11 +39,8 @@ define i32 @ashr_lshr_exact_both(i32 %x, i32 %y) {
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define i32 @ashr_lshr_exact_lshr_only(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_exact_lshr_only(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = lshr exact i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: ret i32 [[RET]]
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; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[CMP1]]
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;
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%cmp = icmp sgt i32 %x, -1
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%l = lshr exact i32 %x, %y
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@ -63,11 +51,8 @@ define i32 @ashr_lshr_exact_lshr_only(i32 %x, i32 %y) {
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define i32 @ashr_lshr2(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr2(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], 5
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: ret i32 [[RET]]
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; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i32 [[CMP1]]
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;
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%cmp = icmp sgt i32 %x, 5
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%l = lshr i32 %x, %y
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@ -78,11 +63,8 @@ define i32 @ashr_lshr2(i32 %x, i32 %y) {
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define <2 x i32> @ashr_lshr_splat_vec(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_splat_vec(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
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; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
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; CHECK-NEXT: ret <2 x i32> [[RET]]
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; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP1]]
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;
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%cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
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%l = lshr <2 x i32> %x, %y
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@ -93,11 +75,8 @@ define <2 x i32> @ashr_lshr_splat_vec(<2 x i32> %x, <2 x i32> %y) {
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define <2 x i32> @ashr_lshr_splat_vec2(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_splat_vec2(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
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; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
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; CHECK-NEXT: ret <2 x i32> [[RET]]
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; CHECK-NEXT: [[CMP1:%.*]] = ashr exact <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP1]]
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;
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%cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
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%l = lshr exact <2 x i32> %x, %y
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@ -108,11 +87,8 @@ define <2 x i32> @ashr_lshr_splat_vec2(<2 x i32> %x, <2 x i32> %y) {
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define <2 x i32> @ashr_lshr_splat_vec3(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_splat_vec3(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
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; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
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; CHECK-NEXT: ret <2 x i32> [[RET]]
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; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP1]]
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;
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%cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
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%l = lshr exact <2 x i32> %x, %y
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@ -123,11 +99,8 @@ define <2 x i32> @ashr_lshr_splat_vec3(<2 x i32> %x, <2 x i32> %y) {
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define <2 x i32> @ashr_lshr_splat_vec4(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_splat_vec4(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 -1>
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; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
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; CHECK-NEXT: ret <2 x i32> [[RET]]
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; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP1]]
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;
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%cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 -1>
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%l = lshr <2 x i32> %x, %y
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@ -138,11 +111,8 @@ define <2 x i32> @ashr_lshr_splat_vec4(<2 x i32> %x, <2 x i32> %y) {
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define <2 x i32> @ashr_lshr_nonsplat_vec(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_nonsplat_vec(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 -1, i32 1>
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; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
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; CHECK-NEXT: ret <2 x i32> [[RET]]
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; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP1]]
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;
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%cmp = icmp sgt <2 x i32> %x, <i32 -1, i32 1>
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%l = lshr <2 x i32> %x, %y
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@ -153,11 +123,8 @@ define <2 x i32> @ashr_lshr_nonsplat_vec(<2 x i32> %x, <2 x i32> %y) {
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define <2 x i32> @ashr_lshr_nonsplat_vec2(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_nonsplat_vec2(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 2, i32 4>
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; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
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; CHECK-NEXT: ret <2 x i32> [[RET]]
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; CHECK-NEXT: [[CMP1:%.*]] = ashr exact <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP1]]
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;
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%cmp = icmp sgt <2 x i32> %x, <i32 2, i32 4>
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%l = lshr exact <2 x i32> %x, %y
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@ -168,11 +135,8 @@ define <2 x i32> @ashr_lshr_nonsplat_vec2(<2 x i32> %x, <2 x i32> %y) {
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define <2 x i32> @ashr_lshr_nonsplat_vec3(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_nonsplat_vec3(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 5, i32 6>
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; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
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; CHECK-NEXT: ret <2 x i32> [[RET]]
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; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP1]]
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;
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%cmp = icmp sgt <2 x i32> %x, <i32 5, i32 6>
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%l = lshr exact <2 x i32> %x, %y
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@ -183,11 +147,8 @@ define <2 x i32> @ashr_lshr_nonsplat_vec3(<2 x i32> %x, <2 x i32> %y) {
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define <2 x i32> @ashr_lshr_nonsplat_vec4(<2 x i32> %x, <2 x i32> %y) {
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; CHECK-LABEL: @ashr_lshr_nonsplat_vec4(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 8, i32 7>
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; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
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; CHECK-NEXT: ret <2 x i32> [[RET]]
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; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i32> [[CMP1]]
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;
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%cmp = icmp sgt <2 x i32> %x, <i32 8, i32 7>
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%l = lshr <2 x i32> %x, %y
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@ -198,11 +159,8 @@ define <2 x i32> @ashr_lshr_nonsplat_vec4(<2 x i32> %x, <2 x i32> %y) {
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define i32 @ashr_lshr_cst(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_cst(
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 1
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], 8
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; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], 8
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
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; CHECK-NEXT: ret i32 [[RET]]
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; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], 8
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; CHECK-NEXT: ret i32 [[CMP1]]
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;
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%cmp = icmp slt i32 %x, 1
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%l = lshr i32 %x, 8
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@ -213,11 +171,8 @@ define i32 @ashr_lshr_cst(i32 %x, i32 %y) {
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define i32 @ashr_lshr_cst2(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_cst2(
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; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X:%.*]], -1
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], 8
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; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], 8
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[L]], i32 [[R]]
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; CHECK-NEXT: ret i32 [[RET]]
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; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], 8
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; CHECK-NEXT: ret i32 [[CMP1]]
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;
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%cmp = icmp sgt i32 %x, -1
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%l = lshr i32 %x, 8
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@ -228,11 +183,8 @@ define i32 @ashr_lshr_cst2(i32 %x, i32 %y) {
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define i32 @ashr_lshr_inv(i32 %x, i32 %y) {
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; CHECK-LABEL: @ashr_lshr_inv(
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 1
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; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
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; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
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; CHECK-NEXT: ret i32 [[RET]]
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; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
|
||||
; CHECK-NEXT: ret i32 [[CMP1]]
|
||||
;
|
||||
%cmp = icmp slt i32 %x, 1
|
||||
%l = lshr i32 %x, %y
|
||||
@ -243,11 +195,8 @@ define i32 @ashr_lshr_inv(i32 %x, i32 %y) {
|
||||
|
||||
define i32 @ashr_lshr_inv2(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: @ashr_lshr_inv2(
|
||||
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[X:%.*]], 7
|
||||
; CHECK-NEXT: [[L:%.*]] = lshr i32 [[X]], [[Y:%.*]]
|
||||
; CHECK-NEXT: [[R:%.*]] = ashr exact i32 [[X]], [[Y]]
|
||||
; CHECK-NEXT: [[RET:%.*]] = select i1 [[CMP]], i32 [[R]], i32 [[L]]
|
||||
; CHECK-NEXT: ret i32 [[RET]]
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = ashr i32 [[X:%.*]], [[Y:%.*]]
|
||||
; CHECK-NEXT: ret i32 [[CMP1]]
|
||||
;
|
||||
%cmp = icmp slt i32 %x, 7
|
||||
%l = lshr i32 %x, %y
|
||||
@ -258,11 +207,8 @@ define i32 @ashr_lshr_inv2(i32 %x, i32 %y) {
|
||||
|
||||
define <2 x i32> @ashr_lshr_inv_splat_vec(<2 x i32> %x, <2 x i32> %y) {
|
||||
; CHECK-LABEL: @ashr_lshr_inv_splat_vec(
|
||||
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 1, i32 1>
|
||||
; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
|
||||
; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
|
||||
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
|
||||
; CHECK-NEXT: ret <2 x i32> [[RET]]
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
|
||||
; CHECK-NEXT: ret <2 x i32> [[CMP1]]
|
||||
;
|
||||
%cmp = icmp slt <2 x i32> %x, <i32 1, i32 1>
|
||||
%l = lshr <2 x i32> %x, %y
|
||||
@ -273,11 +219,8 @@ define <2 x i32> @ashr_lshr_inv_splat_vec(<2 x i32> %x, <2 x i32> %y) {
|
||||
|
||||
define <2 x i32> @ashr_lshr_inv_nonsplat_vec(<2 x i32> %x, <2 x i32> %y) {
|
||||
; CHECK-LABEL: @ashr_lshr_inv_nonsplat_vec(
|
||||
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 4, i32 5>
|
||||
; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
|
||||
; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
|
||||
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
|
||||
; CHECK-NEXT: ret <2 x i32> [[RET]]
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
|
||||
; CHECK-NEXT: ret <2 x i32> [[CMP1]]
|
||||
;
|
||||
%cmp = icmp slt <2 x i32> %x, <i32 4, i32 5>
|
||||
%l = lshr <2 x i32> %x, %y
|
||||
@ -288,11 +231,8 @@ define <2 x i32> @ashr_lshr_inv_nonsplat_vec(<2 x i32> %x, <2 x i32> %y) {
|
||||
|
||||
define <2 x i32> @ashr_lshr_vec_undef(<2 x i32> %x, <2 x i32> %y) {
|
||||
; CHECK-LABEL: @ashr_lshr_vec_undef(
|
||||
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[X:%.*]], <i32 undef, i32 -1>
|
||||
; CHECK-NEXT: [[L:%.*]] = lshr <2 x i32> [[X]], [[Y:%.*]]
|
||||
; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
|
||||
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[L]], <2 x i32> [[R]]
|
||||
; CHECK-NEXT: ret <2 x i32> [[RET]]
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = ashr <2 x i32> [[X:%.*]], [[Y:%.*]]
|
||||
; CHECK-NEXT: ret <2 x i32> [[CMP1]]
|
||||
;
|
||||
%cmp = icmp sgt <2 x i32> %x, <i32 undef, i32 -1>
|
||||
%l = lshr <2 x i32> %x, %y
|
||||
@ -303,11 +243,8 @@ define <2 x i32> @ashr_lshr_vec_undef(<2 x i32> %x, <2 x i32> %y) {
|
||||
|
||||
define <2 x i32> @ashr_lshr_vec_undef2(<2 x i32> %x, <2 x i32> %y) {
|
||||
; CHECK-LABEL: @ashr_lshr_vec_undef2(
|
||||
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 1, i32 undef>
|
||||
; CHECK-NEXT: [[L:%.*]] = lshr exact <2 x i32> [[X]], [[Y:%.*]]
|
||||
; CHECK-NEXT: [[R:%.*]] = ashr exact <2 x i32> [[X]], [[Y]]
|
||||
; CHECK-NEXT: [[RET:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[R]], <2 x i32> [[L]]
|
||||
; CHECK-NEXT: ret <2 x i32> [[RET]]
|
||||
; CHECK-NEXT: [[CMP1:%.*]] = ashr exact <2 x i32> [[X:%.*]], [[Y:%.*]]
|
||||
; CHECK-NEXT: ret <2 x i32> [[CMP1]]
|
||||
;
|
||||
%cmp = icmp slt <2 x i32> %x, <i32 1, i32 undef>
|
||||
%l = lshr exact <2 x i32> %x, %y
|
||||
|
||||
Loading…
Reference in New Issue
Block a user