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random code cleanups.
llvm-svn: 74962
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a754f344b2
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8604f71f91
@ -225,10 +225,10 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
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SDValue RHS = GetScalarizedVector(N->getOperand(1));
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MVT NVT = N->getValueType(0).getVectorElementType();
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MVT SVT = TLI.getSetCCResultType(LHS.getValueType());
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DebugLoc dl = N->getDebugLoc();
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DebugLoc DL = N->getDebugLoc();
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// Turn it into a scalar SETCC.
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SDValue Res = DAG.getNode(ISD::SETCC, dl, SVT, LHS, RHS, N->getOperand(2));
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SDValue Res = DAG.getNode(ISD::SETCC, DL, SVT, LHS, RHS, N->getOperand(2));
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// VSETCC always returns a sign-extended value, while SETCC may not. The
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// SETCC result type may not match the vector element type. Correct these.
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@ -237,19 +237,19 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
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// Ensure the SETCC result is sign-extended.
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if (TLI.getBooleanContents() !=
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TargetLowering::ZeroOrNegativeOneBooleanContent)
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Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, SVT, Res,
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Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
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DAG.getValueType(MVT::i1));
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// Truncate to the final type.
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return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
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} else {
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return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
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}
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// The SETCC result type is smaller than the vector element type.
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// If the SetCC result is not sign-extended, chop it down to MVT::i1.
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if (TLI.getBooleanContents() !=
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TargetLowering::ZeroOrNegativeOneBooleanContent)
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Res = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Res);
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Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
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// Sign extend to the final type.
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return DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Res);
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}
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return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
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}
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SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
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SDValue LHS = GetScalarizedVector(N->getOperand(0));
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@ -278,19 +278,18 @@ bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
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N->dump(&DAG); cerr << "\n";
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#endif
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assert(0 && "Do not know how to scalarize this operator's operand!");
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abort();
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case ISD::BIT_CONVERT:
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Res = ScalarizeVecOp_BIT_CONVERT(N); break;
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Res = ScalarizeVecOp_BIT_CONVERT(N);
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break;
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case ISD::CONCAT_VECTORS:
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Res = ScalarizeVecOp_CONCAT_VECTORS(N); break;
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Res = ScalarizeVecOp_CONCAT_VECTORS(N);
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break;
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case ISD::EXTRACT_VECTOR_ELT:
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Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break;
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Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
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break;
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case ISD::STORE:
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Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
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Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
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break;
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}
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}
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@ -1036,7 +1035,6 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
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if (IdxVal < LoElts)
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return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
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else
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return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
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DAG.getConstant(IdxVal - LoElts,
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Idx.getValueType()));
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@ -1129,8 +1127,11 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
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case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
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case ISD::VECTOR_SHUFFLE:
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Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N)); break;
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case ISD::VSETCC: Res = WidenVecRes_VSETCC(N); break;
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Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
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break;
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case ISD::VSETCC:
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Res = WidenVecRes_VSETCC(N);
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break;
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case ISD::ADD:
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case ISD::AND:
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