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https://github.com/RPCS3/llvm-mirror.git
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[SystemZ] Support conditional indirect sibling calls via BCR
This adds a conditional variant of CallBR instruction, CallBCR. Also, it can be fused with integer comparisons, resulting in one of the new C*BCall instructions. In addition to CallBRCL limitations, this has another one: it won't trigger if the function to call isn't already in %r1 - see f22 in the test for an example (it's also why the loads in tests are volatile). Author: koriakin Differential Revision: http://reviews.llvm.org/D18928 llvm-svn: 265933
This commit is contained in:
Ulrich Weigand
parent
8f03ec0d11
commit
8612094f9a
@ -216,6 +216,85 @@ void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R1D);
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break;
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case SystemZ::CallBCR:
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LoweredMI = MCInstBuilder(SystemZ::BCR)
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.addImm(MI->getOperand(0).getImm())
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.addImm(MI->getOperand(1).getImm())
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.addReg(SystemZ::R1D);
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break;
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case SystemZ::CRBCall:
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LoweredMI = MCInstBuilder(SystemZ::CRB)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addImm(0);
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break;
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case SystemZ::CGRBCall:
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LoweredMI = MCInstBuilder(SystemZ::CGRB)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addImm(0);
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break;
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case SystemZ::CIBCall:
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LoweredMI = MCInstBuilder(SystemZ::CIB)
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.addReg(MI->getOperand(0).getReg())
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.addImm(MI->getOperand(1).getImm())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addImm(0);
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break;
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case SystemZ::CGIBCall:
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LoweredMI = MCInstBuilder(SystemZ::CGIB)
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.addReg(MI->getOperand(0).getReg())
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.addImm(MI->getOperand(1).getImm())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addImm(0);
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break;
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case SystemZ::CLRBCall:
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LoweredMI = MCInstBuilder(SystemZ::CLRB)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addImm(0);
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break;
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case SystemZ::CLGRBCall:
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LoweredMI = MCInstBuilder(SystemZ::CLGRB)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addImm(0);
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break;
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case SystemZ::CLIBCall:
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LoweredMI = MCInstBuilder(SystemZ::CLIB)
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.addReg(MI->getOperand(0).getReg())
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.addImm(MI->getOperand(1).getImm())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addImm(0);
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break;
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case SystemZ::CLGIBCall:
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LoweredMI = MCInstBuilder(SystemZ::CLGIB)
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.addReg(MI->getOperand(0).getReg())
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.addImm(MI->getOperand(1).getImm())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addImm(0);
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break;
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case SystemZ::TLS_GDCALL:
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LoweredMI = MCInstBuilder(SystemZ::BRASL)
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.addReg(SystemZ::R14D)
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@ -392,6 +392,9 @@ fuseCompareAndBranch(MachineInstr *Compare,
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case SystemZ::CondReturn:
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Type = SystemZII::CompareAndReturn;
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break;
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case SystemZ::CallBCR:
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Type = SystemZII::CompareAndSibcall;
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break;
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default:
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return false;
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}
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@ -412,19 +415,24 @@ fuseCompareAndBranch(MachineInstr *Compare,
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(SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI)))
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return false;
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// Read the branch mask and target (if applicable).
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// Read the branch mask, target (if applicable), regmask (if applicable).
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MachineOperand CCMask(MBBI->getOperand(1));
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assert((CCMask.getImm() & ~SystemZ::CCMASK_ICMP) == 0 &&
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"Invalid condition-code mask for integer comparison");
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// This is only valid for CompareAndBranch.
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MachineOperand Target(MBBI->getOperand(
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Type == SystemZII::CompareAndBranch ? 2 : 0));
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const uint32_t *RegMask;
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if (Type == SystemZII::CompareAndSibcall)
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RegMask = MBBI->getOperand(2).getRegMask();
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// Clear out all current operands.
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int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI);
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assert(CCUse >= 0 && "BRC/BCR must use CC");
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Branch->RemoveOperand(CCUse);
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if (Type == SystemZII::CompareAndBranch)
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// Remove target (branch) or regmask (sibcall).
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if (Type == SystemZII::CompareAndBranch ||
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Type == SystemZII::CompareAndSibcall)
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Branch->RemoveOperand(2);
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Branch->RemoveOperand(1);
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Branch->RemoveOperand(0);
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@ -444,6 +452,9 @@ fuseCompareAndBranch(MachineInstr *Compare,
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.addReg(SystemZ::CC, RegState::ImplicitDefine);
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}
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if (Type == SystemZII::CompareAndSibcall)
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MIB.addRegMask(RegMask);
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// Clear any intervening kills of SrcReg and SrcReg2.
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MBBI = Compare;
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for (++MBBI; MBBI != MBBE; ++MBBI) {
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@ -511,7 +511,8 @@ bool SystemZInstrInfo::isPredicable(MachineInstr &MI) const {
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if (STI.hasLoadStoreOnCond() && getConditionalMove(Opcode))
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return true;
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if (Opcode == SystemZ::Return ||
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Opcode == SystemZ::CallJG)
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Opcode == SystemZ::CallJG ||
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Opcode == SystemZ::CallBR)
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return true;
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return false;
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}
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@ -585,6 +586,16 @@ bool SystemZInstrInfo::PredicateInstruction(
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.addReg(SystemZ::CC, RegState::Implicit);
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return true;
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}
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if (Opcode == SystemZ::CallBR) {
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const uint32_t *RegMask = MI.getOperand(0).getRegMask();
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MI.RemoveOperand(0);
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MI.setDesc(get(SystemZ::CallBCR));
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MachineInstrBuilder(*MI.getParent()->getParent(), MI)
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.addImm(CCValid).addImm(CCMask)
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.addRegMask(RegMask)
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.addReg(SystemZ::CC, RegState::Implicit);
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return true;
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}
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return false;
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}
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@ -1348,6 +1359,27 @@ unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
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default:
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return 0;
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}
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case SystemZII::CompareAndSibcall:
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switch (Opcode) {
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case SystemZ::CR:
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return SystemZ::CRBCall;
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case SystemZ::CGR:
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return SystemZ::CGRBCall;
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case SystemZ::CHI:
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return SystemZ::CIBCall;
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case SystemZ::CGHI:
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return SystemZ::CGIBCall;
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case SystemZ::CLR:
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return SystemZ::CLRBCall;
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case SystemZ::CLGR:
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return SystemZ::CLGRBCall;
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case SystemZ::CLFI:
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return SystemZ::CLIBCall;
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case SystemZ::CLGFI:
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return SystemZ::CLGIBCall;
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default:
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return 0;
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}
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}
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return 0;
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}
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@ -119,7 +119,10 @@ enum CompareAndBranchType {
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CompareAndBranch,
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// Indirect branch, used for return - CRBReturn etc.
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CompareAndReturn
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CompareAndReturn,
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// Indirect branch, used for sibcall - CRBCall etc.
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CompareAndSibcall
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};
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} // end namespace SystemZII
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@ -327,10 +327,26 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
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def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>;
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}
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let CCMaskFirst = 1, isCall = 1, isReturn = 1 in
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let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in {
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def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1,
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pcrel32:$I2), []>;
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let Uses = [R1D] in
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def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>;
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}
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// Fused compare and conditional sibling calls.
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let isCall = 1, isTerminator = 1, isReturn = 1, Uses = [R1D] in {
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def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
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def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
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def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>;
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def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>;
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def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>;
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def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>;
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def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>;
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def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>;
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}
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// TLS calls. These will be lowered into a call to __tls_get_offset,
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// with an extra relocation specifying the TLS symbol.
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let isCall = 1, Defs = [R14D, CC] in {
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467
test/CodeGen/SystemZ/call-05.ll
Normal file
467
test/CodeGen/SystemZ/call-05.ll
Normal file
@ -0,0 +1,467 @@
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; Test conditional sibling calls.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@var = global i32 1;
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@fun_a = global void()* null;
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@fun_b = global void()* null;
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@fun_c = global void(i32)* null;
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; Check a conditional sibling call.
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define void @f1(i32 %val1, i32 %val2) {
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; CHECK-LABEL: f1:
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; CHECK: crbl %r2, %r3, 0(%r1)
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; CHECK: br %r14
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%fun_a = load volatile void() *, void()** @fun_a;
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%cond = icmp slt i32 %val1, %val2;
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br i1 %cond, label %a, label %b;
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a:
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tail call void %fun_a()
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ret void
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b:
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store i32 1, i32 *@var;
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ret void
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}
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; Check a conditional sibling call when there are two possibilities.
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define void @f2(i32 %val1, i32 %val2) {
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; CHECK-LABEL: f2:
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; CHECK: crbl %r2, %r3, 0(%r1)
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; CHECK: br %r1
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%fun_a = load volatile void() *, void()** @fun_a;
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%fun_b = load volatile void() *, void()** @fun_b;
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%cond = icmp slt i32 %val1, %val2;
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br i1 %cond, label %a, label %b;
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a:
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tail call void %fun_a()
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ret void
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b:
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tail call void %fun_b()
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ret void
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}
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; Check a conditional sibling call with an argument - not supported.
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define void @f3(i32 %val1, i32 %val2) {
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; CHECK-LABEL: f3:
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; CHECK: crjhe %r2, %r3
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; CHECK: br %r1
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; CHECK: br %r14
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%fun_c = load volatile void(i32) *, void(i32)** @fun_c;
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%cond = icmp slt i32 %val1, %val2;
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br i1 %cond, label %a, label %b;
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a:
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tail call void %fun_c(i32 1)
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ret void
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b:
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store i32 1, i32 *@var;
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ret void
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}
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; Check a conditional sibling call - unsigned compare.
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define void @f4(i32 %val1, i32 %val2) {
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; CHECK-LABEL: f4:
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; CHECK: clrbl %r2, %r3, 0(%r1)
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; CHECK: br %r14
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%fun_a = load volatile void() *, void()** @fun_a;
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%cond = icmp ult i32 %val1, %val2;
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br i1 %cond, label %a, label %b;
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a:
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tail call void %fun_a()
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ret void
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b:
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store i32 1, i32 *@var;
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ret void
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}
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; Check a conditional sibling call - 64-bit compare.
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define void @f5(i64 %val1, i64 %val2) {
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; CHECK-LABEL: f5:
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; CHECK: cgrbl %r2, %r3, 0(%r1)
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; CHECK: br %r14
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%fun_a = load volatile void() *, void()** @fun_a;
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%cond = icmp slt i64 %val1, %val2;
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br i1 %cond, label %a, label %b;
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a:
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tail call void %fun_a()
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ret void
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b:
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store i32 1, i32 *@var;
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ret void
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}
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; Check a conditional sibling call - unsigned 64-bit compare.
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define void @f6(i64 %val1, i64 %val2) {
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; CHECK-LABEL: f6:
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; CHECK: clgrbl %r2, %r3, 0(%r1)
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; CHECK: br %r14
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%fun_a = load volatile void() *, void()** @fun_a;
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%cond = icmp ult i64 %val1, %val2;
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br i1 %cond, label %a, label %b;
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a:
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tail call void %fun_a()
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ret void
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b:
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store i32 1, i32 *@var;
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ret void
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}
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; Check a conditional sibling call - less-equal compare.
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define void @f7(i32 %val1, i32 %val2) {
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; CHECK-LABEL: f7:
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; CHECK: crble %r2, %r3, 0(%r1)
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; CHECK: br %r14
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%fun_a = load volatile void() *, void()** @fun_a;
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%cond = icmp sle i32 %val1, %val2;
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br i1 %cond, label %a, label %b;
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a:
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tail call void %fun_a()
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ret void
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b:
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store i32 1, i32 *@var;
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ret void
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}
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; Check a conditional sibling call - high compare.
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define void @f8(i32 %val1, i32 %val2) {
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; CHECK-LABEL: f8:
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; CHECK: crbh %r2, %r3, 0(%r1)
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; CHECK: br %r14
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%fun_a = load volatile void() *, void()** @fun_a;
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%cond = icmp sgt i32 %val1, %val2;
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br i1 %cond, label %a, label %b;
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a:
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tail call void %fun_a()
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ret void
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b:
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store i32 1, i32 *@var;
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ret void
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}
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; Check a conditional sibling call - high-equal compare.
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define void @f9(i32 %val1, i32 %val2) {
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; CHECK-LABEL: f9:
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; CHECK: crbhe %r2, %r3, 0(%r1)
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; CHECK: br %r14
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%fun_a = load volatile void() *, void()** @fun_a;
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%cond = icmp sge i32 %val1, %val2;
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br i1 %cond, label %a, label %b;
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a:
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tail call void %fun_a()
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ret void
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b:
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store i32 1, i32 *@var;
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ret void
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}
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; Check a conditional sibling call - equal compare.
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define void @f10(i32 %val1, i32 %val2) {
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; CHECK-LABEL: f10:
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; CHECK: crbe %r2, %r3, 0(%r1)
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; CHECK: br %r14
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%fun_a = load volatile void() *, void()** @fun_a;
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%cond = icmp eq i32 %val1, %val2;
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br i1 %cond, label %a, label %b;
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a:
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tail call void %fun_a()
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ret void
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b:
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store i32 1, i32 *@var;
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ret void
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}
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; Check a conditional sibling call - unequal compare.
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define void @f11(i32 %val1, i32 %val2) {
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; CHECK-LABEL: f11:
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; CHECK: crblh %r2, %r3, 0(%r1)
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; CHECK: br %r14
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%fun_a = load volatile void() *, void()** @fun_a;
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%cond = icmp ne i32 %val1, %val2;
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br i1 %cond, label %a, label %b;
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a:
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tail call void %fun_a()
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ret void
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b:
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store i32 1, i32 *@var;
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ret void
|
||||
}
|
||||
|
||||
; Check a conditional sibling call - immediate slt.
|
||||
define void @f12(i32 %val1) {
|
||||
; CHECK-LABEL: f12:
|
||||
; CHECK: cible %r2, 4, 0(%r1)
|
||||
; CHECK: br %r14
|
||||
%fun_a = load volatile void() *, void()** @fun_a;
|
||||
%cond = icmp slt i32 %val1, 5;
|
||||
br i1 %cond, label %a, label %b;
|
||||
|
||||
a:
|
||||
tail call void %fun_a()
|
||||
ret void
|
||||
|
||||
b:
|
||||
store i32 1, i32 *@var;
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check a conditional sibling call - immediate sle.
|
||||
define void @f13(i32 %val1) {
|
||||
; CHECK-LABEL: f13:
|
||||
; CHECK: cible %r2, 5, 0(%r1)
|
||||
; CHECK: br %r14
|
||||
%fun_a = load volatile void() *, void()** @fun_a;
|
||||
%cond = icmp sle i32 %val1, 5;
|
||||
br i1 %cond, label %a, label %b;
|
||||
|
||||
a:
|
||||
tail call void %fun_a()
|
||||
ret void
|
||||
|
||||
b:
|
||||
store i32 1, i32 *@var;
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check a conditional sibling call - immediate sgt.
|
||||
define void @f14(i32 %val1) {
|
||||
; CHECK-LABEL: f14:
|
||||
; CHECK: cibhe %r2, 6, 0(%r1)
|
||||
; CHECK: br %r14
|
||||
%fun_a = load volatile void() *, void()** @fun_a;
|
||||
%cond = icmp sgt i32 %val1, 5;
|
||||
br i1 %cond, label %a, label %b;
|
||||
|
||||
a:
|
||||
tail call void %fun_a()
|
||||
ret void
|
||||
|
||||
b:
|
||||
store i32 1, i32 *@var;
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check a conditional sibling call - immediate sge.
|
||||
define void @f15(i32 %val1) {
|
||||
; CHECK-LABEL: f15:
|
||||
; CHECK: cibhe %r2, 5, 0(%r1)
|
||||
; CHECK: br %r14
|
||||
%fun_a = load volatile void() *, void()** @fun_a;
|
||||
%cond = icmp sge i32 %val1, 5;
|
||||
br i1 %cond, label %a, label %b;
|
||||
|
||||
a:
|
||||
tail call void %fun_a()
|
||||
ret void
|
||||
|
||||
b:
|
||||
store i32 1, i32 *@var;
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check a conditional sibling call - immediate eq.
|
||||
define void @f16(i32 %val1) {
|
||||
; CHECK-LABEL: f16:
|
||||
; CHECK: cibe %r2, 5, 0(%r1)
|
||||
; CHECK: br %r14
|
||||
%fun_a = load volatile void() *, void()** @fun_a;
|
||||
%cond = icmp eq i32 %val1, 5;
|
||||
br i1 %cond, label %a, label %b;
|
||||
|
||||
a:
|
||||
tail call void %fun_a()
|
||||
ret void
|
||||
|
||||
b:
|
||||
store i32 1, i32 *@var;
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check a conditional sibling call - immediate ne.
|
||||
define void @f17(i32 %val1) {
|
||||
; CHECK-LABEL: f17:
|
||||
; CHECK: ciblh %r2, 5, 0(%r1)
|
||||
; CHECK: br %r14
|
||||
%fun_a = load volatile void() *, void()** @fun_a;
|
||||
%cond = icmp ne i32 %val1, 5;
|
||||
br i1 %cond, label %a, label %b;
|
||||
|
||||
a:
|
||||
tail call void %fun_a()
|
||||
ret void
|
||||
|
||||
b:
|
||||
store i32 1, i32 *@var;
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check a conditional sibling call - immediate ult.
|
||||
define void @f18(i32 %val1) {
|
||||
; CHECK-LABEL: f18:
|
||||
; CHECK: clible %r2, 4, 0(%r1)
|
||||
; CHECK: br %r14
|
||||
%fun_a = load volatile void() *, void()** @fun_a;
|
||||
%cond = icmp ult i32 %val1, 5;
|
||||
br i1 %cond, label %a, label %b;
|
||||
|
||||
a:
|
||||
tail call void %fun_a()
|
||||
ret void
|
||||
|
||||
b:
|
||||
store i32 1, i32 *@var;
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check a conditional sibling call - immediate 64-bit slt.
|
||||
define void @f19(i64 %val1) {
|
||||
; CHECK-LABEL: f19:
|
||||
; CHECK: cgible %r2, 4, 0(%r1)
|
||||
; CHECK: br %r14
|
||||
%fun_a = load volatile void() *, void()** @fun_a;
|
||||
%cond = icmp slt i64 %val1, 5;
|
||||
br i1 %cond, label %a, label %b;
|
||||
|
||||
a:
|
||||
tail call void %fun_a()
|
||||
ret void
|
||||
|
||||
b:
|
||||
store i32 1, i32 *@var;
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check a conditional sibling call - immediate 64-bit ult.
|
||||
define void @f20(i64 %val1) {
|
||||
; CHECK-LABEL: f20:
|
||||
; CHECK: clgible %r2, 4, 0(%r1)
|
||||
; CHECK: br %r14
|
||||
%fun_a = load volatile void() *, void()** @fun_a;
|
||||
%cond = icmp ult i64 %val1, 5;
|
||||
br i1 %cond, label %a, label %b;
|
||||
|
||||
a:
|
||||
tail call void %fun_a()
|
||||
ret void
|
||||
|
||||
b:
|
||||
store i32 1, i32 *@var;
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check a conditional sibling call to an argument - will fail due to
|
||||
; intervening lgr.
|
||||
define void @f21(i32 %val1, i32 %val2, void()* %fun) {
|
||||
; CHECK-LABEL: f21:
|
||||
; CHECK: crjhe %r2, %r3
|
||||
; CHECK: lgr %r1, %r4
|
||||
; CHECK: br %r1
|
||||
; CHECK: br %r14
|
||||
%cond = icmp slt i32 %val1, %val2;
|
||||
br i1 %cond, label %a, label %b;
|
||||
|
||||
a:
|
||||
tail call void %fun()
|
||||
ret void
|
||||
|
||||
b:
|
||||
store i32 1, i32 *@var;
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check a conditional sibling call - float olt compare.
|
||||
define void @f22(float %val1, float %val2) {
|
||||
; CHECK-LABEL: f22:
|
||||
; CHECK: cebr %f0, %f2
|
||||
; CHECK: blr %r1
|
||||
; CHECK: br %r14
|
||||
%fun_a = load volatile void() *, void()** @fun_a;
|
||||
%cond = fcmp olt float %val1, %val2;
|
||||
br i1 %cond, label %a, label %b;
|
||||
|
||||
a:
|
||||
tail call void %fun_a()
|
||||
ret void
|
||||
|
||||
b:
|
||||
store i32 1, i32 *@var;
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check a conditional sibling call - float ult compare.
|
||||
define void @f23(float %val1, float %val2) {
|
||||
; CHECK-LABEL: f23:
|
||||
; CHECK: cebr %f0, %f2
|
||||
; CHECK: bnher %r1
|
||||
; CHECK: br %r14
|
||||
%fun_a = load volatile void() *, void()** @fun_a;
|
||||
%cond = fcmp ult float %val1, %val2;
|
||||
br i1 %cond, label %a, label %b;
|
||||
|
||||
a:
|
||||
tail call void %fun_a()
|
||||
ret void
|
||||
|
||||
b:
|
||||
store i32 1, i32 *@var;
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check a conditional sibling call - float ord compare.
|
||||
define void @f24(float %val1, float %val2) {
|
||||
; CHECK-LABEL: f24:
|
||||
; CHECK: cebr %f0, %f2
|
||||
; CHECK: bnor %r1
|
||||
; CHECK: br %r14
|
||||
%fun_a = load volatile void() *, void()** @fun_a;
|
||||
%cond = fcmp ord float %val1, %val2;
|
||||
br i1 %cond, label %a, label %b;
|
||||
|
||||
a:
|
||||
tail call void %fun_a()
|
||||
ret void
|
||||
|
||||
b:
|
||||
store i32 1, i32 *@var;
|
||||
ret void
|
||||
}
|
||||
|
||||
; Check a conditional sibling call - float uno compare.
|
||||
define void @f25(float %val1, float %val2) {
|
||||
; CHECK-LABEL: f25:
|
||||
; CHECK: cebr %f0, %f2
|
||||
; CHECK: bor %r1
|
||||
; CHECK: br %r14
|
||||
%fun_a = load volatile void() *, void()** @fun_a;
|
||||
%cond = fcmp uno float %val1, %val2;
|
||||
br i1 %cond, label %a, label %b;
|
||||
|
||||
a:
|
||||
tail call void %fun_a()
|
||||
ret void
|
||||
|
||||
b:
|
||||
store i32 1, i32 *@var;
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user