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R600: BB operand support for SI

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Patch by: Christian König

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
llvm-svn: 170342
This commit is contained in:
Tom Stellard 2012-12-17 15:14:54 +00:00
parent 6817104534
commit 861d1ea443
4 changed files with 27 additions and 4 deletions
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10
lib/Target/R600/AMDGPUMCInstLower.cpp
View File

@ -21,11 +21,14 @@
#include "llvm/Constants.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/Support/ErrorHandling.h"
using namespace llvm;
AMDGPUMCInstLower::AMDGPUMCInstLower() { }
AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx):
Ctx(ctx)
{ }
void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());
@ -50,13 +53,16 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
case MachineOperand::MO_Register:
MCOp = MCOperand::CreateReg(MO.getReg());
break;
case MachineOperand::MO_MachineBasicBlock:
MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
MO.getMBB()->getSymbol(), Ctx));
}
OutMI.addOperand(MCOp);
}
}
void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
AMDGPUMCInstLower MCInstLowering;
AMDGPUMCInstLower MCInstLowering(OutContext);
if (MI->isBundle()) {
const MachineBasicBlock *MBB = MI->getParent();

5
lib/Target/R600/AMDGPUMCInstLower.h
View File

@ -14,12 +14,15 @@
namespace llvm {
class MCInst;
class MCContext;
class MachineInstr;
class AMDGPUMCInstLower {
MCContext &Ctx;
public:
AMDGPUMCInstLower();
AMDGPUMCInstLower(MCContext &ctx);
/// \brief Lower a MachineInstr to an MCInst
void lower(const MachineInstr *MI, MCInst &OutMI) const;

10
lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
View File

@ -47,7 +47,7 @@ public:
virtual AMDGPUMCObjectWriter *createObjectWriter(raw_ostream &OS) const;
virtual unsigned getNumFixupKinds() const { return 0; };
virtual void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
uint64_t Value) const { assert(!"Not implemented"); }
uint64_t Value) const;
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
const MCInstFragment *DF,
const MCAsmLayout &Layout) const {
@ -80,3 +80,11 @@ AMDGPUMCObjectWriter * AMDGPUAsmBackend::createObjectWriter(
raw_ostream &OS) const {
return new AMDGPUMCObjectWriter(OS);
}
void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
unsigned DataSize, uint64_t Value) const {
uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset());
assert(Fixup.getKind() == FK_PCRel_4);
*Dst = (Value - 4) / 4;
}

6
lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp
View File

@ -21,6 +21,7 @@
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCFixup.h"
#include "llvm/Support/raw_ostream.h"
#define VGPR_BIT(src_idx) (1ULL << (9 * src_idx - 1))
@ -149,6 +150,11 @@ uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
} Imm;
Imm.F = MO.getFPImm();
return Imm.I;
} else if (MO.isExpr()) {
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(FK_PCRel_4);
Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
return 0;
} else{
llvm_unreachable("Encoding of this operand type is not supported yet.");
}