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Revert "[LoopDeletion] Break backedge if we can prove that the loop is exited on 1st iteration"
This reverts commit 2531fd70d19aa5d61feb533bbdeee7717a4129eb due to performance regression on the PPC buildbot.
This commit is contained in:
Matt Morehouse
parent
77c89471fd
commit
86272fe99b
@ -17,7 +17,6 @@
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/GlobalsModRef.h"
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#include "llvm/Analysis/LoopIterator.h"
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#include "llvm/Analysis/LoopPass.h"
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#include "llvm/Analysis/MemorySSA.h"
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#include "llvm/Analysis/OptimizationRemarkEmitter.h"
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@ -136,155 +135,6 @@ static bool isLoopNeverExecuted(Loop *L) {
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return true;
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}
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static const SCEV *
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getSCEVOnFirstIteration(Value *V, Loop *L, ScalarEvolution &SE,
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DenseMap<Value *, const SCEV *> &FirstIterSCEV) {
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// Fist, check in cache.
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auto Existing = FirstIterSCEV.find(V);
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if (Existing != FirstIterSCEV.end())
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return Existing->second;
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const SCEV *S = nullptr;
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// TODO: Once ScalarEvolution supports getValueOnNthIteration for anything
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// else but AddRecs, it's a good use case for it. So far, just consider some
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// simple cases, like arithmetic operations.
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Value *LHS, *RHS;
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using namespace PatternMatch;
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if (match(V, m_Add(m_Value(LHS), m_Value(RHS)))) {
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const SCEV *LHSS = getSCEVOnFirstIteration(LHS, L, SE, FirstIterSCEV);
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const SCEV *RHSS = getSCEVOnFirstIteration(RHS, L, SE, FirstIterSCEV);
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S = SE.getAddExpr(LHSS, RHSS);
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} else if (match(V, m_Sub(m_Value(LHS), m_Value(RHS)))) {
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const SCEV *LHSS = getSCEVOnFirstIteration(LHS, L, SE, FirstIterSCEV);
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const SCEV *RHSS = getSCEVOnFirstIteration(RHS, L, SE, FirstIterSCEV);
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S = SE.getMinusSCEV(LHSS, RHSS);
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} else if (match(V, m_Mul(m_Value(LHS), m_Value(RHS)))) {
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const SCEV *LHSS = getSCEVOnFirstIteration(LHS, L, SE, FirstIterSCEV);
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const SCEV *RHSS = getSCEVOnFirstIteration(RHS, L, SE, FirstIterSCEV);
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S = SE.getMulExpr(LHSS, RHSS);
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} else
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S = SE.getSCEV(V);
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assert(S && "Case not handled?");
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FirstIterSCEV[V] = S;
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return S;
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}
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// Try to prove that one of conditions that dominates the latch must exit on 1st
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// iteration.
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static bool canProveExitOnFirstIteration(Loop *L, DominatorTree &DT,
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ScalarEvolution &SE, LoopInfo &LI) {
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BasicBlock *Latch = L->getLoopLatch();
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if (!Latch)
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return false;
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LoopBlocksRPO RPOT(L);
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RPOT.perform(&LI);
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BasicBlock *Header = L->getHeader();
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// Blocks that are reachable on the 1st iteration.
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SmallPtrSet<BasicBlock *, 4> LiveBlocks;
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// Edges that are reachable on the 1st iteration.
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DenseSet<BasicBlockEdge> LiveEdges;
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LiveBlocks.insert(L->getHeader());
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auto MarkLiveEdge = [&](BasicBlock *From, BasicBlock *To) {
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assert(LiveBlocks.count(From) && "Must be live!");
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LiveBlocks.insert(To);
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LiveEdges.insert({ From, To });
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};
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auto MarkAllSuccessorsLive = [&](BasicBlock *BB) {
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for (auto *Succ : successors(BB))
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MarkLiveEdge(BB, Succ);
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};
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// Check if there is only one predecessor on 1st iteration. Note that because
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// we iterate in RPOT, we have already visited all its (non-latch)
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// predecessors.
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auto GetSolePredecessorOnFirstIteration = [&](BasicBlock * BB)->BasicBlock * {
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if (BB == Header)
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return L->getLoopPredecessor();
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BasicBlock *OnlyPred = nullptr;
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for (auto *Pred : predecessors(BB))
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if (OnlyPred != Pred && LiveEdges.count({ Pred, BB })) {
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// 2 live preds.
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if (OnlyPred)
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return nullptr;
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OnlyPred = Pred;
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}
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assert(OnlyPred && "No live predecessors?");
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return OnlyPred;
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};
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DenseMap<Value *, const SCEV *> FirstIterSCEV;
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// Use the following algorithm to prove we never take the latch on the 1st
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// iteration:
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// 1. Traverse in topological order, so that whenever we visit a block, all
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// its predecessors are already visited.
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// 2. If we can prove that the block may have only 1 predecessor on the 1st
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// iteration, map all its phis onto input from this predecessor.
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// 3a. If we can prove which successor of out block is taken on the 1st
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// iteration, mark this successor live.
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// 3b. If we cannot prove it, conservatively assume that all successors are
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// live.
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for (auto *BB : RPOT) {
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// This block is not reachable on the 1st iterations.
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if (!LiveBlocks.count(BB))
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continue;
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// Skip inner loops.
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if (LI.getLoopFor(BB) != L) {
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MarkAllSuccessorsLive(BB);
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continue;
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}
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// If this block has only one live pred, map its phis onto their SCEVs.
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if (auto *OnlyPred = GetSolePredecessorOnFirstIteration(BB))
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for (auto &PN : BB->phis()) {
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if (!SE.isSCEVable(PN.getType()))
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continue;
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auto *Incoming = PN.getIncomingValueForBlock(OnlyPred);
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if (DT.dominates(Incoming, BB->getTerminator())) {
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const SCEV *IncSCEV =
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getSCEVOnFirstIteration(Incoming, L, SE, FirstIterSCEV);
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FirstIterSCEV[&PN] = IncSCEV;
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}
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}
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using namespace PatternMatch;
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ICmpInst::Predicate Pred;
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Value *LHS, *RHS;
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const BasicBlock *IfTrue, *IfFalse;
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// TODO: Handle switches.
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if (!match(BB->getTerminator(),
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m_Br(m_ICmp(Pred, m_Value(LHS), m_Value(RHS)),
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m_BasicBlock(IfTrue), m_BasicBlock(IfFalse)))) {
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MarkAllSuccessorsLive(BB);
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continue;
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}
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if (!SE.isSCEVable(LHS->getType())) {
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MarkAllSuccessorsLive(BB);
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continue;
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}
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// Can we prove constant true or false for this condition?
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const SCEV *LHSS = getSCEVOnFirstIteration(LHS, L, SE, FirstIterSCEV);
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const SCEV *RHSS = getSCEVOnFirstIteration(RHS, L, SE, FirstIterSCEV);
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if (SE.isKnownPredicateAt(Pred, LHSS, RHSS, BB->getTerminator()))
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MarkLiveEdge(BB, BB->getTerminator()->getSuccessor(0));
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else if (SE.isKnownPredicateAt(ICmpInst::getInversePredicate(Pred), LHSS,
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RHSS, BB->getTerminator()))
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MarkLiveEdge(BB, BB->getTerminator()->getSuccessor(1));
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else
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MarkAllSuccessorsLive(BB);
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}
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// We can break the latch if it wasn't live.
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return !LiveEdges.count({ Latch, Header });
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}
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/// If we can prove the backedge is untaken, remove it. This destroys the
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/// loop, but leaves the (now trivially loop invariant) control flow and
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/// side effects (if any) in place.
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@ -298,7 +148,7 @@ breakBackedgeIfNotTaken(Loop *L, DominatorTree &DT, ScalarEvolution &SE,
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return LoopDeletionResult::Unmodified;
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auto *BTC = SE.getBackedgeTakenCount(L);
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if (!BTC->isZero() && !canProveExitOnFirstIteration(L, DT, SE, LI))
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if (!BTC->isZero())
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return LoopDeletionResult::Unmodified;
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breakLoopBackedge(L, DT, SE, LI, MSSA);
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@ -7,6 +7,7 @@
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; and therefore prove that %sum.next = %sum + %sub = %sum + %limit - %sum = %limit,
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; and predicate is false.
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; TODO: We can break the backedge here.
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define i32 @test_ne(i32 %limit) {
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; CHECK-LABEL: @test_ne(
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; CHECK-NEXT: entry:
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@ -15,19 +16,17 @@ define i32 @test_ne(i32 %limit) {
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; CHECK: loop.preheader:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[LIMIT]], [[SUM]]
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; CHECK-NEXT: [[IS_POSITIVE:%.*]] = icmp sgt i32 [[SUB]], 0
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; CHECK-NEXT: br i1 [[IS_POSITIVE]], label [[BACKEDGE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK-NEXT: br i1 [[IS_POSITIVE]], label [[BACKEDGE]], label [[IF_FALSE:%.*]]
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; CHECK: if.false:
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; CHECK-NEXT: br label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[MERGE_PHI:%.*]] = phi i32 [ 0, [[IF_FALSE]] ], [ [[SUB]], [[LOOP]] ]
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; CHECK-NEXT: [[SUM_NEXT:%.*]] = add i32 [[SUM]], [[MERGE_PHI]]
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; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[MERGE_PHI]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ne i32 [[SUM_NEXT]], [[LIMIT]]
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[BACKEDGE_LOOP_CRIT_EDGE:%.*]], label [[DONE:%.*]]
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; CHECK: backedge.loop_crit_edge:
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; CHECK-NEXT: unreachable
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[DONE:%.*]]
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; CHECK: done:
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; CHECK-NEXT: [[SUM_NEXT_LCSSA:%.*]] = phi i32 [ [[SUM_NEXT]], [[BACKEDGE]] ]
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; CHECK-NEXT: ret i32 [[SUM_NEXT_LCSSA]]
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@ -61,6 +60,7 @@ failure:
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unreachable
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}
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; TODO: We can break the backedge here.
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define i32 @test_slt(i32 %limit) {
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; CHECK-LABEL: @test_slt(
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; CHECK-NEXT: entry:
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@ -69,19 +69,17 @@ define i32 @test_slt(i32 %limit) {
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; CHECK: loop.preheader:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[LIMIT]], [[SUM]]
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; CHECK-NEXT: [[IS_POSITIVE:%.*]] = icmp sgt i32 [[SUB]], 0
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; CHECK-NEXT: br i1 [[IS_POSITIVE]], label [[BACKEDGE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK-NEXT: br i1 [[IS_POSITIVE]], label [[BACKEDGE]], label [[IF_FALSE:%.*]]
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; CHECK: if.false:
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; CHECK-NEXT: br label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[MERGE_PHI:%.*]] = phi i32 [ 0, [[IF_FALSE]] ], [ [[SUB]], [[LOOP]] ]
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; CHECK-NEXT: [[SUM_NEXT:%.*]] = add i32 [[SUM]], [[MERGE_PHI]]
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; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[MERGE_PHI]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp slt i32 [[SUM_NEXT]], [[LIMIT]]
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[BACKEDGE_LOOP_CRIT_EDGE:%.*]], label [[DONE:%.*]]
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; CHECK: backedge.loop_crit_edge:
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; CHECK-NEXT: unreachable
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[DONE:%.*]]
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; CHECK: done:
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; CHECK-NEXT: [[SUM_NEXT_LCSSA:%.*]] = phi i32 [ [[SUM_NEXT]], [[BACKEDGE]] ]
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; CHECK-NEXT: ret i32 [[SUM_NEXT_LCSSA]]
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@ -115,6 +113,7 @@ failure:
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unreachable
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}
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; TODO: We can break the backedge here.
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define i32 @test_ult(i32 %limit) {
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; CHECK-LABEL: @test_ult(
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; CHECK-NEXT: entry:
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@ -123,19 +122,17 @@ define i32 @test_ult(i32 %limit) {
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; CHECK: loop.preheader:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[LIMIT]], [[SUM]]
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; CHECK-NEXT: [[IS_POSITIVE:%.*]] = icmp sgt i32 [[SUB]], 0
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; CHECK-NEXT: br i1 [[IS_POSITIVE]], label [[BACKEDGE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK-NEXT: br i1 [[IS_POSITIVE]], label [[BACKEDGE]], label [[IF_FALSE:%.*]]
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; CHECK: if.false:
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; CHECK-NEXT: br label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[MERGE_PHI:%.*]] = phi i32 [ 0, [[IF_FALSE]] ], [ [[SUB]], [[LOOP]] ]
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; CHECK-NEXT: [[SUM_NEXT:%.*]] = add i32 [[SUM]], [[MERGE_PHI]]
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; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[MERGE_PHI]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ult i32 [[SUM_NEXT]], [[LIMIT]]
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[BACKEDGE_LOOP_CRIT_EDGE:%.*]], label [[DONE:%.*]]
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; CHECK: backedge.loop_crit_edge:
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; CHECK-NEXT: unreachable
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[DONE:%.*]]
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; CHECK: done:
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; CHECK-NEXT: [[SUM_NEXT_LCSSA:%.*]] = phi i32 [ [[SUM_NEXT]], [[BACKEDGE]] ]
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; CHECK-NEXT: ret i32 [[SUM_NEXT_LCSSA]]
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@ -169,6 +166,7 @@ failure:
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unreachable
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}
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; TODO: We can break the backedge here.
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define i32 @test_sgt(i32 %limit) {
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; CHECK-LABEL: @test_sgt(
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; CHECK-NEXT: entry:
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@ -177,19 +175,17 @@ define i32 @test_sgt(i32 %limit) {
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; CHECK: loop.preheader:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[LIMIT]], [[SUM]]
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; CHECK-NEXT: [[IS_POSITIVE:%.*]] = icmp sgt i32 [[SUB]], 0
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; CHECK-NEXT: br i1 [[IS_POSITIVE]], label [[BACKEDGE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK-NEXT: br i1 [[IS_POSITIVE]], label [[BACKEDGE]], label [[IF_FALSE:%.*]]
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; CHECK: if.false:
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; CHECK-NEXT: br label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[MERGE_PHI:%.*]] = phi i32 [ 0, [[IF_FALSE]] ], [ [[SUB]], [[LOOP]] ]
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; CHECK-NEXT: [[SUM_NEXT:%.*]] = add i32 [[SUM]], [[MERGE_PHI]]
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; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[MERGE_PHI]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp sgt i32 [[SUM_NEXT]], [[LIMIT]]
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[BACKEDGE_LOOP_CRIT_EDGE:%.*]], label [[DONE:%.*]]
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; CHECK: backedge.loop_crit_edge:
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; CHECK-NEXT: unreachable
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[DONE:%.*]]
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; CHECK: done:
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; CHECK-NEXT: [[SUM_NEXT_LCSSA:%.*]] = phi i32 [ [[SUM_NEXT]], [[BACKEDGE]] ]
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; CHECK-NEXT: ret i32 [[SUM_NEXT_LCSSA]]
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@ -223,6 +219,7 @@ failure:
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unreachable
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}
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; TODO: We can break the backedge here.
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define i32 @test_ugt(i32 %limit) {
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; CHECK-LABEL: @test_ugt(
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; CHECK-NEXT: entry:
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@ -231,19 +228,17 @@ define i32 @test_ugt(i32 %limit) {
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; CHECK: loop.preheader:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[LIMIT]], [[SUM]]
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; CHECK-NEXT: [[IS_POSITIVE:%.*]] = icmp sgt i32 [[SUB]], 0
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; CHECK-NEXT: br i1 [[IS_POSITIVE]], label [[BACKEDGE:%.*]], label [[IF_FALSE:%.*]]
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; CHECK-NEXT: br i1 [[IS_POSITIVE]], label [[BACKEDGE]], label [[IF_FALSE:%.*]]
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; CHECK: if.false:
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; CHECK-NEXT: br label [[BACKEDGE]]
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; CHECK: backedge:
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; CHECK-NEXT: [[MERGE_PHI:%.*]] = phi i32 [ 0, [[IF_FALSE]] ], [ [[SUB]], [[LOOP]] ]
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; CHECK-NEXT: [[SUM_NEXT:%.*]] = add i32 [[SUM]], [[MERGE_PHI]]
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; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[MERGE_PHI]]
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; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ugt i32 [[SUM_NEXT]], [[LIMIT]]
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[BACKEDGE_LOOP_CRIT_EDGE:%.*]], label [[DONE:%.*]]
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; CHECK: backedge.loop_crit_edge:
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; CHECK-NEXT: unreachable
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[DONE:%.*]]
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; CHECK: done:
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; CHECK-NEXT: [[SUM_NEXT_LCSSA:%.*]] = phi i32 [ [[SUM_NEXT]], [[BACKEDGE]] ]
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; CHECK-NEXT: ret i32 [[SUM_NEXT_LCSSA]]
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@ -277,6 +272,7 @@ failure:
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unreachable
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}
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; TODO: We can break the backedge here.
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define i32 @test_multiple_pred(i32 %limit) {
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; CHECK-LABEL: @test_multiple_pred(
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; CHECK-NEXT: entry:
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@ -285,24 +281,22 @@ define i32 @test_multiple_pred(i32 %limit) {
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; CHECK: loop.preheader:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ [[SUM_NEXT:%.*]], [[BACKEDGE:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[LIMIT]], [[SUM]]
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; CHECK-NEXT: [[IS_POSITIVE:%.*]] = icmp sgt i32 [[SUB]], 0
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||||
; CHECK-NEXT: br i1 [[IS_POSITIVE]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
|
||||
; CHECK: if.true:
|
||||
; CHECK-NEXT: switch i32 [[LIMIT]], label [[FAILURE_LOOPEXIT:%.*]] [
|
||||
; CHECK-NEXT: i32 100, label [[BACKEDGE:%.*]]
|
||||
; CHECK-NEXT: i32 100, label [[BACKEDGE]]
|
||||
; CHECK-NEXT: i32 200, label [[BACKEDGE]]
|
||||
; CHECK-NEXT: ]
|
||||
; CHECK: if.false:
|
||||
; CHECK-NEXT: br label [[BACKEDGE]]
|
||||
; CHECK: backedge:
|
||||
; CHECK-NEXT: [[MERGE_PHI:%.*]] = phi i32 [ 0, [[IF_FALSE]] ], [ [[SUB]], [[IF_TRUE]] ], [ [[SUB]], [[IF_TRUE]] ]
|
||||
; CHECK-NEXT: [[SUM_NEXT:%.*]] = add i32 [[SUM]], [[MERGE_PHI]]
|
||||
; CHECK-NEXT: [[SUM_NEXT]] = add i32 [[SUM]], [[MERGE_PHI]]
|
||||
; CHECK-NEXT: [[LOOP_COND:%.*]] = icmp ne i32 [[SUM_NEXT]], [[LIMIT]]
|
||||
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[BACKEDGE_LOOP_CRIT_EDGE:%.*]], label [[DONE:%.*]]
|
||||
; CHECK: backedge.loop_crit_edge:
|
||||
; CHECK-NEXT: unreachable
|
||||
; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[DONE:%.*]]
|
||||
; CHECK: done:
|
||||
; CHECK-NEXT: [[SUM_NEXT_LCSSA:%.*]] = phi i32 [ [[SUM_NEXT]], [[BACKEDGE]] ]
|
||||
; CHECK-NEXT: ret i32 [[SUM_NEXT_LCSSA]]
|
||||
|
||||
@ -50,7 +50,7 @@ define void @test2_sideeffect_in_outer(i64 %N, i64 %M, %pair_t* %ptr) willreturn
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]
|
||||
; CHECK: outer.header:
|
||||
; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ]
|
||||
; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
|
||||
; CHECK-NEXT: br label [[INNER:%.*]]
|
||||
; CHECK: inner:
|
||||
; CHECK-NEXT: [[INNER_IV:%.*]] = phi i64 [ 0, [[OUTER_HEADER]] ], [ [[INNER_IV_NEXT:%.*]], [[INNER]] ]
|
||||
@ -60,15 +60,13 @@ define void @test2_sideeffect_in_outer(i64 %N, i64 %M, %pair_t* %ptr) willreturn
|
||||
; CHECK-NEXT: [[V_1:%.*]] = extractvalue [[PAIR_T]] [[P]], 1
|
||||
; CHECK-NEXT: [[INNER_EC:%.*]] = icmp ult i64 [[V_0]], [[V_1]]
|
||||
; CHECK-NEXT: [[INNER_IV_NEXT]] = add i64 [[INNER_IV]], 1
|
||||
; CHECK-NEXT: br i1 [[INNER_EC]], label [[OUTER_LATCH:%.*]], label [[INNER]]
|
||||
; CHECK-NEXT: br i1 [[INNER_EC]], label [[OUTER_LATCH]], label [[INNER]]
|
||||
; CHECK: outer.latch:
|
||||
; CHECK-NEXT: [[LCSSA:%.*]] = phi i64 [ [[V_1]], [[INNER]] ]
|
||||
; CHECK-NEXT: [[OUTER_EC:%.*]] = icmp ult i64 [[OUTER_IV]], [[LCSSA]]
|
||||
; CHECK-NEXT: [[OUTER_IV_NEXT:%.*]] = add i64 [[OUTER_IV]], 1
|
||||
; CHECK-NEXT: [[OUTER_IV_NEXT]] = add i64 [[OUTER_IV]], 1
|
||||
; CHECK-NEXT: call void @sideeffect()
|
||||
; CHECK-NEXT: br i1 [[OUTER_EC]], label [[EXIT:%.*]], label [[OUTER_LATCH_OUTER_HEADER_CRIT_EDGE:%.*]]
|
||||
; CHECK: outer.latch.outer.header_crit_edge:
|
||||
; CHECK-NEXT: unreachable
|
||||
; CHECK-NEXT: br i1 [[OUTER_EC]], label [[EXIT:%.*]], label [[OUTER_HEADER]]
|
||||
; CHECK: exit:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
@ -107,7 +105,7 @@ define void @test3_sideeffect_in_inner(i64 %N, i64 %M, %pair_t* %ptr) willreturn
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: br label [[OUTER_HEADER:%.*]]
|
||||
; CHECK: outer.header:
|
||||
; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ]
|
||||
; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[OUTER_IV_NEXT:%.*]], [[OUTER_LATCH:%.*]] ]
|
||||
; CHECK-NEXT: br label [[INNER:%.*]]
|
||||
; CHECK: inner:
|
||||
; CHECK-NEXT: [[INNER_IV:%.*]] = phi i64 [ 0, [[OUTER_HEADER]] ], [ [[INNER_IV_NEXT:%.*]], [[INNER]] ]
|
||||
@ -118,14 +116,12 @@ define void @test3_sideeffect_in_inner(i64 %N, i64 %M, %pair_t* %ptr) willreturn
|
||||
; CHECK-NEXT: [[INNER_EC:%.*]] = icmp ult i64 [[V_0]], [[V_1]]
|
||||
; CHECK-NEXT: [[INNER_IV_NEXT]] = add i64 [[INNER_IV]], 1
|
||||
; CHECK-NEXT: call void @sideeffect()
|
||||
; CHECK-NEXT: br i1 [[INNER_EC]], label [[OUTER_LATCH:%.*]], label [[INNER]]
|
||||
; CHECK-NEXT: br i1 [[INNER_EC]], label [[OUTER_LATCH]], label [[INNER]]
|
||||
; CHECK: outer.latch:
|
||||
; CHECK-NEXT: [[LCSSA:%.*]] = phi i64 [ [[V_1]], [[INNER]] ]
|
||||
; CHECK-NEXT: [[OUTER_EC:%.*]] = icmp ult i64 [[OUTER_IV]], [[LCSSA]]
|
||||
; CHECK-NEXT: [[OUTER_IV_NEXT:%.*]] = add i64 [[OUTER_IV]], 1
|
||||
; CHECK-NEXT: br i1 [[OUTER_EC]], label [[EXIT:%.*]], label [[OUTER_LATCH_OUTER_HEADER_CRIT_EDGE:%.*]]
|
||||
; CHECK: outer.latch.outer.header_crit_edge:
|
||||
; CHECK-NEXT: unreachable
|
||||
; CHECK-NEXT: [[OUTER_IV_NEXT]] = add i64 [[OUTER_IV]], 1
|
||||
; CHECK-NEXT: br i1 [[OUTER_EC]], label [[EXIT:%.*]], label [[OUTER_HEADER]]
|
||||
; CHECK: exit:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
|
||||
@ -161,16 +161,14 @@ define void @test_multi_exit3(i1 %cond1) {
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: br label [[LOOP:%.*]]
|
||||
; CHECK: loop:
|
||||
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ]
|
||||
; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_INC:%.*]], [[LATCH:%.*]] ]
|
||||
; CHECK-NEXT: store i32 0, i32* @G, align 4
|
||||
; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LATCH:%.*]], label [[EXIT:%.*]]
|
||||
; CHECK-NEXT: br i1 [[COND1:%.*]], label [[LATCH]], label [[EXIT:%.*]]
|
||||
; CHECK: latch:
|
||||
; CHECK-NEXT: store i32 1, i32* @G, align 4
|
||||
; CHECK-NEXT: [[IV_INC:%.*]] = add i32 [[IV]], 1
|
||||
; CHECK-NEXT: [[IV_INC]] = add i32 [[IV]], 1
|
||||
; CHECK-NEXT: [[BE_TAKEN:%.*]] = icmp ne i32 [[IV_INC]], 1
|
||||
; CHECK-NEXT: br i1 [[BE_TAKEN]], label [[LATCH_LOOP_CRIT_EDGE:%.*]], label [[EXIT]]
|
||||
; CHECK: latch.loop_crit_edge:
|
||||
; CHECK-NEXT: unreachable
|
||||
; CHECK-NEXT: br i1 [[BE_TAKEN]], label [[LOOP]], label [[EXIT]]
|
||||
; CHECK: exit:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user