RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 19:12:56 +02:00
Code Issues Projects Releases Wiki Activity

[mips] Add precondition asserts to the expandLoadInst/expandStoreInst. NFC

Browse Source 
llvm-svn: 333162
This commit is contained in:
Simon Atanasyan 2018-05-24 07:36:06 +00:00
parent 5b2855c72c
commit 8630b238fa
1 changed files with 23 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -3565,10 +3565,15 @@ void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
void MipsAsmParser::expandLoadInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI, bool IsImmOpnd) {
MipsTargetStreamer &TOut = getTargetStreamer();
const MCOperand &DstRegOp = Inst.getOperand(0);
assert(DstRegOp.isReg() && "expected register operand kind");
const MCOperand &BaseRegOp = Inst.getOperand(1);
assert(BaseRegOp.isReg() && "expected register operand kind");
const MCOperand &OffsetOp = Inst.getOperand(2);
unsigned DstReg = Inst.getOperand(0).getReg();
unsigned BaseReg = Inst.getOperand(1).getReg();
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned DstReg = DstRegOp.getReg();
unsigned BaseReg = BaseRegOp.getReg();
const MCInstrDesc &Desc = getInstDesc(Inst.getOpcode());
int16_t DstRegClass = Desc.OpInfo[0].RegClass;
@ -3581,8 +3586,7 @@ void MipsAsmParser::expandLoadInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
// Try to use DstReg as the temporary.
if (IsGPR && (BaseReg != DstReg)) {
TOut.emitLoadWithImmOffset(Inst.getOpcode(), DstReg, BaseReg,
Inst.getOperand(2).getImm(), DstReg, IDLoc,
STI);
OffsetOp.getImm(), DstReg, IDLoc, STI);
return;
}
@ -3593,11 +3597,12 @@ void MipsAsmParser::expandLoadInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
return;
TOut.emitLoadWithImmOffset(Inst.getOpcode(), DstReg, BaseReg,
Inst.getOperand(2).getImm(), ATReg, IDLoc, STI);
OffsetOp.getImm(), ATReg, IDLoc, STI);
return;
}
const MCExpr *ExprOffset = Inst.getOperand(2).getExpr();
assert(OffsetOp.isExpr() && "expected expression operand kind");
const MCExpr *ExprOffset = OffsetOp.getExpr();
MCOperand LoOperand = MCOperand::createExpr(
MipsMCExpr::create(MipsMCExpr::MEK_LO, ExprOffset, getContext()));
MCOperand HiOperand = MCOperand::createExpr(
@ -3623,14 +3628,19 @@ void MipsAsmParser::expandLoadInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
void MipsAsmParser::expandStoreInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
const MCSubtargetInfo *STI,
bool IsImmOpnd) {
MipsTargetStreamer &TOut = getTargetStreamer();
const MCOperand &SrcRegOp = Inst.getOperand(0);
assert(SrcRegOp.isReg() && "expected register operand kind");
const MCOperand &BaseRegOp = Inst.getOperand(1);
assert(BaseRegOp.isReg() && "expected register operand kind");
const MCOperand &OffsetOp = Inst.getOperand(2);
unsigned SrcReg = Inst.getOperand(0).getReg();
unsigned BaseReg = Inst.getOperand(1).getReg();
MipsTargetStreamer &TOut = getTargetStreamer();
unsigned SrcReg = SrcRegOp.getReg();
unsigned BaseReg = BaseRegOp.getReg();
if (IsImmOpnd) {
TOut.emitStoreWithImmOffset(Inst.getOpcode(), SrcReg, BaseReg,
Inst.getOperand(2).getImm(),
OffsetOp.getImm(),
[&]() { return getATReg(IDLoc); }, IDLoc, STI);
return;
}
@ -3639,7 +3649,8 @@ void MipsAsmParser::expandStoreInst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
if (!ATReg)
return;
const MCExpr *ExprOffset = Inst.getOperand(2).getExpr();
assert(OffsetOp.isExpr() && "expected expression operand kind");
const MCExpr *ExprOffset = OffsetOp.getExpr();
MCOperand LoOperand = MCOperand::createExpr(
MipsMCExpr::create(MipsMCExpr::MEK_LO, ExprOffset, getContext()));
MCOperand HiOperand = MCOperand::createExpr(