RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-23 13:02:52 +02:00
Code Issues Projects Releases Wiki Activity

Add UDIV, SDIV, and a few variants of WR.

Browse Source 
llvm-svn: 12733
This commit is contained in:
Brian Gaeke 2004-04-07 04:01:00 +00:00
parent 0d35bd3ca9
commit 8651efab54
1 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -94,6 +94,10 @@ def SUBrr : F3_1<2, 0b000100, "sub">;
def UMULrr : F3_1<2, 0b001010, "umul">;
def SMULrr : F3_1<2, 0b001011, "smul">;
// Section B.19 - Divide Instructions, p. 115
def UDIVrr: F3_1<2, 0b001110, "udiv">;
def SDIVrr: F3_1<2, 0b001111, "sdiv">;
// Section B.20 - SAVE and RESTORE, p. 117
def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r
@ -114,3 +118,7 @@ def CALL : InstV8 {
def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
def JMPLri : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
// Section B.29 - Write State Register Instructions, p. 133
let rd = 0 in
def WRYrr : F3_1<2, 0b110000, "wr">; // Special case of WRASR
def WRASRrr : F3_1<2, 0b110000, "wr">; // Special reg = reg ^ reg