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Revert "[ms-cxxabi] Add a new calling convention that swaps 'this' and 'sret'"

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This reverts commit r200561.

This calling convention was an attempt to match the MSVC C++ ABI for
methods that return structures by value.  This solution didn't scale,
because it would have required splitting every CC available on Windows
into two: one for methods and one for free functions.

Now that we can put sret on the second arg (r208453), and Clang does
that (r208458), revert this hack.

llvm-svn: 208459
This commit is contained in:
Reid Kleckner 2014-05-09 22:56:42 +00:00
parent f6b4cc99cd
commit 86ad66783f
10 changed files with 2 additions and 124 deletions
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2
docs/BitCodeFormat.rst
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@ -747,8 +747,6 @@ function. The operand fields are:
* ``arm_apcscc``: code 66
* ``arm_aapcscc``: code 67
* ``arm_aapcs_vfpcc``: code 68
* ``x86_thiscallcc``: code 70
* ``x86_cdeclmethodcc``: code 80
* isproto*: Non-zero if this entry represents a declaration rather than a
definition

4
docs/CodeGenerator.rst
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@ -2145,10 +2145,6 @@ The following target-specific calling conventions are known to backend:
others via stack. Callee is responsible for stack cleaning. This convention is
used by MSVC by default for methods in its ABI (CC ID = 70).
* **X86_CDeclMethod** --- Identical to the standard x86_32 C calling convention,
except that an sret paramter, if present, is placed on the stack after the
second parameter, which must an integer or pointer. (CC ID = 80).
.. _X86 addressing mode:
Representing X86 addressing modes in MachineInstrs

8
include/llvm/IR/CallingConv.h
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@ -137,13 +137,7 @@ namespace CallingConv {
/// convention differs from the more common \c X86_64_SysV convention
/// in a number of ways, most notably in that XMM registers used to pass
/// arguments are shadowed by GPRs, and vice versa.
X86_64_Win64 = 79,
/// \brief The calling convention used for __cdecl methods on win32.
/// Differs from the C calling convention only in that the order of the
/// first parameter and the sret parameter are swapped.
X86_CDeclMethod = 80
X86_64_Win64 = 79
};
} // End CallingConv namespace

1
lib/AsmParser/LLLexer.cpp
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@ -555,7 +555,6 @@ lltok::Kind LLLexer::LexIdentifier() {
KEYWORD(x86_stdcallcc);
KEYWORD(x86_fastcallcc);
KEYWORD(x86_thiscallcc);
KEYWORD(x86_cdeclmethodcc);
KEYWORD(arm_apcscc);
KEYWORD(arm_aapcscc);
KEYWORD(arm_aapcs_vfpcc);

2
lib/AsmParser/LLParser.cpp
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@ -1381,7 +1381,6 @@ bool LLParser::ParseOptionalDLLStorageClass(unsigned &Res) {
/// ::= 'x86_stdcallcc'
/// ::= 'x86_fastcallcc'
/// ::= 'x86_thiscallcc'
/// ::= 'x86_cdeclmethodcc'
/// ::= 'arm_apcscc'
/// ::= 'arm_aapcscc'
/// ::= 'arm_aapcs_vfpcc'
@ -1407,7 +1406,6 @@ bool LLParser::ParseOptionalCallingConv(CallingConv::ID &CC) {
case lltok::kw_x86_stdcallcc: CC = CallingConv::X86_StdCall; break;
case lltok::kw_x86_fastcallcc: CC = CallingConv::X86_FastCall; break;
case lltok::kw_x86_thiscallcc: CC = CallingConv::X86_ThisCall; break;
case lltok::kw_x86_cdeclmethodcc:CC = CallingConv::X86_CDeclMethod; break;
case lltok::kw_arm_apcscc: CC = CallingConv::ARM_APCS; break;
case lltok::kw_arm_aapcscc: CC = CallingConv::ARM_AAPCS; break;
case lltok::kw_arm_aapcs_vfpcc:CC = CallingConv::ARM_AAPCS_VFP; break;

2
lib/AsmParser/LLToken.h
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@ -88,7 +88,7 @@ namespace lltok {
kw_cc, kw_ccc, kw_fastcc, kw_coldcc,
kw_intel_ocl_bicc,
kw_x86_stdcallcc, kw_x86_fastcallcc, kw_x86_thiscallcc, kw_x86_cdeclmethodcc,
kw_x86_stdcallcc, kw_x86_fastcallcc, kw_x86_thiscallcc,
kw_arm_apcscc, kw_arm_aapcscc, kw_arm_aapcs_vfpcc,
kw_msp430_intrcc,
kw_ptx_kernel, kw_ptx_device,

1
lib/IR/AsmWriter.cpp
View File

@ -78,7 +78,6 @@ static void PrintCallingConv(unsigned cc, raw_ostream &Out) {
case CallingConv::X86_StdCall: Out << "x86_stdcallcc"; break;
case CallingConv::X86_FastCall: Out << "x86_fastcallcc"; break;
case CallingConv::X86_ThisCall: Out << "x86_thiscallcc"; break;
case CallingConv::X86_CDeclMethod:Out << "x86_cdeclmethodcc"; break;
case CallingConv::Intel_OCL_BI: Out << "intel_ocl_bicc"; break;
case CallingConv::ARM_APCS: Out << "arm_apcscc"; break;
case CallingConv::ARM_AAPCS: Out << "arm_aapcscc"; break;

27
lib/Target/X86/X86CallingConv.h
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@ -29,33 +29,6 @@ inline bool CC_X86_AnyReg_Error(unsigned &, MVT &, MVT &,
return false;
}
inline bool CC_X86_CDeclMethod_SRet(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags, CCState &State) {
// Swap the order of the first two parameters if the first parameter is sret.
if (ArgFlags.isSRet()) {
assert(ValNo == 0);
assert(ValVT == MVT::i32);
State.AllocateStack(8, 4);
State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 4, LocVT, LocInfo));
// Indicate that we need to swap the order of the first and second
// parameters by "allocating" register zero. There are no register
// parameters with cdecl methods, so we can use this to communicate to the
// next call.
State.AllocateReg(1);
return true;
} else if (ValNo == 1 && State.isAllocated(1)) {
assert(ValVT == MVT::i32 && "non-i32-sized this param unsupported");
// Stack was already allocated while processing sret.
State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 0, LocVT, LocInfo));
return true;
}
// All other args use the C calling convention.
return false;
}
} // End llvm namespace
#endif

10
lib/Target/X86/X86CallingConv.td
View File

@ -485,15 +485,6 @@ def CC_X86_32_ThisCall_Win : CallingConv<[
CCDelegateTo<CC_X86_32_ThisCall_Common>
]>;
def CC_X86_CDeclMethod : CallingConv<[
// Promote i8/i16 arguments to i32.
CCIfType<[i8, i16], CCPromoteToType<i32>>,
CCCustom<"CC_X86_CDeclMethod_SRet">,
CCDelegateTo<CC_X86_32_Common>
]>;
def CC_X86_32_ThisCall : CallingConv<[
CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>,
CCDelegateTo<CC_X86_32_ThisCall_Win>
@ -583,7 +574,6 @@ def CC_Intel_OCL_BI : CallingConv<[
def CC_X86_32 : CallingConv<[
CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>,
CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>,
CCIfCC<"CallingConv::X86_CDeclMethod", CCDelegateTo<CC_X86_CDeclMethod>>,
CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>,
CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>,
CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>,

69
test/CodeGen/X86/cdecl-method-return.ll
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@ -1,69 +0,0 @@
; RUN: llc < %s -mtriple=i686-pc-win32 -mcpu=core2 | FileCheck %s
; The sret flag causes the first two parameters to be reordered on the stack.
define x86_cdeclmethodcc void @foo(i32* sret %dst, i32* %src) {
%v = load i32* %src
store i32 %v, i32* %dst
ret void
}
; CHECK-LABEL: _foo:
; CHECK: movl 8(%esp), %[[dst:[^ ]*]]
; CHECK: movl 4(%esp), %[[src:[^ ]*]]
; CHECK: movl (%[[src]]), %[[v:[^ ]*]]
; CHECK: movl %[[v]], (%[[dst]])
; CHECK: retl
define i32 @bar() {
%src = alloca i32
%dst = alloca i32
store i32 42, i32* %src
call x86_cdeclmethodcc void @foo(i32* sret %dst, i32* %src)
%v = load i32* %dst
ret i32 %v
}
; CHECK-LABEL: _bar:
; CHECK: movl $42, [[src:[^,]*]]
; CHECK: leal [[src]], %[[reg:[^ ]*]]
; CHECK: movl %[[reg]], (%esp)
; CHECK: leal [[dst:[^,]*]], %[[reg:[^ ]*]]
; CHECK: movl %[[reg]], 4(%esp)
; CHECK: calll _foo
; CHECK: movl [[dst]], %eax
; CHECK: retl
; If we don't have the sret flag, parameters are not reordered.
define x86_cdeclmethodcc void @baz(i32* %dst, i32* %src) {
%v = load i32* %src
store i32 %v, i32* %dst
ret void
}
; CHECK-LABEL: _baz:
; CHECK: movl 4(%esp), %[[dst:[^ ]*]]
; CHECK: movl 8(%esp), %[[src:[^ ]*]]
; CHECK: movl (%[[src]]), %[[v:[^ ]*]]
; CHECK: movl %[[v]], (%[[dst]])
; CHECK: retl
define i32 @qux() {
%src = alloca i32
%dst = alloca i32
store i32 42, i32* %src
call x86_cdeclmethodcc void @baz(i32* %dst, i32* %src)
%v = load i32* %dst
ret i32 %v
}
; CHECK-LABEL: _qux:
; CHECK: movl $42, [[src:[^,]*]]
; CHECK: leal [[src]], %[[reg:[^ ]*]]
; CHECK: movl %[[reg]], 4(%esp)
; CHECK: leal [[dst:[^,]*]], %[[reg:[^ ]*]]
; CHECK: movl %[[reg]], (%esp)
; CHECK: calll _baz
; CHECK: movl [[dst]], %eax
; CHECK: retl