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Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer.

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llvm-svn: 186869
This commit is contained in:
Craig Topper 2013-07-22 20:46:37 +00:00
parent 062dd20303
commit 86b83be14d
2 changed files with 43 additions and 43 deletions
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56
lib/Target/X86/X86InstrInfo.td
View File

@ -1979,22 +1979,22 @@ def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
// div and idiv aliases for explicit A register.
def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
def : InstAlias<"div{b}\t{$src, %al|AL, $src}", (DIV8r GR8 :$src)>;
def : InstAlias<"div{w}\t{$src, %ax|AX, $src}", (DIV16r GR16:$src)>;
def : InstAlias<"div{l}\t{$src, %eax|EAX, $src}", (DIV32r GR32:$src)>;
def : InstAlias<"div{q}\t{$src, %rax|RAX, $src}", (DIV64r GR64:$src)>;
def : InstAlias<"div{b}\t{$src, %al|AL, $src}", (DIV8m i8mem :$src)>;
def : InstAlias<"div{w}\t{$src, %ax|AX, $src}", (DIV16m i16mem:$src)>;
def : InstAlias<"div{l}\t{$src, %eax|EAX, $src}", (DIV32m i32mem:$src)>;
def : InstAlias<"div{q}\t{$src, %rax|RAX, $src}", (DIV64m i64mem:$src)>;
def : InstAlias<"idiv{b}\t{$src, %al|AL, $src}", (IDIV8r GR8 :$src)>;
def : InstAlias<"idiv{w}\t{$src, %ax|AX, $src}", (IDIV16r GR16:$src)>;
def : InstAlias<"idiv{l}\t{$src, %eax|EAX, $src}", (IDIV32r GR32:$src)>;
def : InstAlias<"idiv{q}\t{$src, %rax|RAX, $src}", (IDIV64r GR64:$src)>;
def : InstAlias<"idiv{b}\t{$src, %al|AL, $src}", (IDIV8m i8mem :$src)>;
def : InstAlias<"idiv{w}\t{$src, %ax|AX, $src}", (IDIV16m i16mem:$src)>;
def : InstAlias<"idiv{l}\t{$src, %eax|EAX, $src}", (IDIV32m i32mem:$src)>;
def : InstAlias<"idiv{q}\t{$src, %rax|RAX, $src}", (IDIV64m i64mem:$src)>;
@ -2076,12 +2076,12 @@ def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
// inb %dx -> inb %al, %dx
def : InstAlias<"inb %dx", (IN8rr)>;
def : InstAlias<"inw %dx", (IN16rr)>;
def : InstAlias<"inl %dx", (IN32rr)>;
def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
def : InstAlias<"inb\t{%dx|DX}", (IN8rr), 0>;
def : InstAlias<"inw\t{%dx|DX}", (IN16rr), 0>;
def : InstAlias<"inl\t{%dx|DX}", (IN32rr), 0>;
def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
@ -2130,12 +2130,12 @@ def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
// Note: No GR32->GR64 movzx form.
// outb %dx -> outb %al, %dx
def : InstAlias<"outb %dx", (OUT8rr)>;
def : InstAlias<"outw %dx", (OUT16rr)>;
def : InstAlias<"outl %dx", (OUT32rr)>;
def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
def : InstAlias<"outb\t{%dx|DX}", (OUT8rr), 0>;
def : InstAlias<"outw\t{%dx|DX}", (OUT16rr), 0>;
def : InstAlias<"outl\t{%dx|DX}", (OUT32rr), 0>;
def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity

30
test/MC/X86/x86-64.s
View File

@ -241,10 +241,10 @@ cmovnzq %rbx, %rax
// rdar://8407928
// CHECK: inb $127, %al
// CHECK: inw %dx
// CHECK: inw %dx, %ax
// CHECK: outb %al, $127
// CHECK: outw %dx
// CHECK: inl %dx
// CHECK: outw %ax, %dx
// CHECK: inl %dx, %eax
inb $0x7f
inw %dx
outb $0x7f
@ -253,12 +253,12 @@ inl %dx
// PR8114
// CHECK: outb %dx
// CHECK: outb %dx
// CHECK: outw %dx
// CHECK: outw %dx
// CHECK: outl %dx
// CHECK: outl %dx
// CHECK: outb %al, %dx
// CHECK: outb %al, %dx
// CHECK: outw %ax, %dx
// CHECK: outw %ax, %dx
// CHECK: outl %eax, %dx
// CHECK: outl %eax, %dx
out %al, (%dx)
outb %al, (%dx)
@ -267,12 +267,12 @@ outw %ax, (%dx)
out %eax, (%dx)
outl %eax, (%dx)
// CHECK: inb %dx
// CHECK: inb %dx
// CHECK: inw %dx
// CHECK: inw %dx
// CHECK: inl %dx
// CHECK: inl %dx
// CHECK: inb %dx, %al
// CHECK: inb %dx, %al
// CHECK: inw %dx, %ax
// CHECK: inw %dx, %ax
// CHECK: inl %dx, %eax
// CHECK: inl %dx, %eax
in (%dx), %al
inb (%dx), %al