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[mips] Implement sle/sleu pseudo instructions
The `sle/sleu Dst, Src1, Src2/Imm` pseudo instructions set register `Dst` to 1 if register `Src1` is less than or equal `Src2/Imm` and to 0 otherwise.
This commit is contained in:
Simon Atanasyan
parent
927588cd01
commit
86c237d29d
@ -298,6 +298,12 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI);
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bool expandRotation(MCInst &Inst, SMLoc IDLoc,
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MCStreamer &Out, const MCSubtargetInfo *STI);
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bool expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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@ -2515,6 +2521,14 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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case Mips::SGTImm64:
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case Mips::SGTUImm64:
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return expandSgtImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::SLE:
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case Mips::SLEU:
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return expandSle(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::SLEImm:
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case Mips::SLEUImm:
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case Mips::SLEImm64:
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case Mips::SLEUImm64:
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return expandSleImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::SLTImm64:
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if (isInt<16>(Inst.getOperand(2).getImm())) {
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Inst.setOpcode(Mips::SLTi64);
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@ -4639,6 +4653,88 @@ bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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return false;
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}
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bool MipsAsmParser::expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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MipsTargetStreamer &TOut = getTargetStreamer();
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assert(Inst.getNumOperands() == 3 && "Invalid operand count");
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assert(Inst.getOperand(0).isReg() &&
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Inst.getOperand(1).isReg() &&
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Inst.getOperand(2).isReg() && "Invalid instruction operand.");
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unsigned DstReg = Inst.getOperand(0).getReg();
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unsigned SrcReg = Inst.getOperand(1).getReg();
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unsigned OpReg = Inst.getOperand(2).getReg();
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unsigned OpCode;
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warnIfNoMacro(IDLoc);
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switch (Inst.getOpcode()) {
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case Mips::SLE:
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OpCode = Mips::SLT;
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break;
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case Mips::SLEU:
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OpCode = Mips::SLTu;
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break;
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default:
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llvm_unreachable("unexpected 'sge' opcode");
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}
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// $SrcReg <= $OpReg is equal to (not ($OpReg < $SrcReg))
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TOut.emitRRR(OpCode, DstReg, OpReg, SrcReg, IDLoc, STI);
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TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
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return false;
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}
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bool MipsAsmParser::expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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MipsTargetStreamer &TOut = getTargetStreamer();
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assert(Inst.getNumOperands() == 3 && "Invalid operand count");
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assert(Inst.getOperand(0).isReg() &&
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Inst.getOperand(1).isReg() &&
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Inst.getOperand(2).isImm() && "Invalid instruction operand.");
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unsigned DstReg = Inst.getOperand(0).getReg();
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unsigned SrcReg = Inst.getOperand(1).getReg();
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int64_t ImmValue = Inst.getOperand(2).getImm();
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unsigned OpRegCode;
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warnIfNoMacro(IDLoc);
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switch (Inst.getOpcode()) {
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case Mips::SLEImm:
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case Mips::SLEImm64:
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OpRegCode = Mips::SLT;
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break;
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case Mips::SLEUImm:
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case Mips::SLEUImm64:
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OpRegCode = Mips::SLTu;
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break;
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default:
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llvm_unreachable("unexpected 'sge' opcode with immediate");
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}
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// $SrcReg <= Imm is equal to (not (Imm < $SrcReg))
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unsigned ImmReg = DstReg;
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if (DstReg == SrcReg) {
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unsigned ATReg = getATReg(Inst.getLoc());
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if (!ATReg)
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return true;
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ImmReg = ATReg;
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}
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if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
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false, IDLoc, Out, STI))
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return true;
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TOut.emitRRR(OpRegCode, DstReg, ImmReg, SrcReg, IDLoc, STI);
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TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
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return false;
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}
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bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
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MCStreamer &Out,
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const MCSubtargetInfo *STI) {
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@ -1248,5 +1248,19 @@ def : MipsInstAlias<"sgtu $rs, $imm", (SGTUImm64 GPR64Opnd:$rs,
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GPR64Opnd:$rs,
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imm64:$imm), 0>, GPR_64;
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def SLEImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
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(ins GPR64Opnd:$rs, imm64:$imm),
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"sle\t$rd, $rs, $imm">, GPR_64;
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def : MipsInstAlias<"sle $rs, $imm", (SLEImm64 GPR64Opnd:$rs,
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GPR64Opnd:$rs,
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imm64:$imm), 0>, GPR_64;
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def SLEUImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
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(ins GPR64Opnd:$rs, imm64:$imm),
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"sleu\t$rd, $rs, $imm">, GPR_64;
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def : MipsInstAlias<"sleu $rs, $imm", (SLEUImm64 GPR64Opnd:$rs,
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GPR64Opnd:$rs,
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imm64:$imm), 0>, GPR_64;
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def : MipsInstAlias<"rdhwr $rt, $rs",
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(RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0), 1>, GPR_64;
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@ -2736,6 +2736,34 @@ let AdditionalPredicates = [NotInMicroMips] in {
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uimm32_coerced:$imm), 0>,
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GPR_32;
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def SLE : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
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(ins GPR32Opnd:$rs, GPR32Opnd:$rt),
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"sle\t$rd, $rs, $rt">, ISA_MIPS1;
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def : MipsInstAlias<"sle $rs, $rt",
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(SLE GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,
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ISA_MIPS1;
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def SLEImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
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(ins GPR32Opnd:$rs, simm32:$imm),
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"sle\t$rd, $rs, $imm">, GPR_32;
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def : MipsInstAlias<"sle $rs, $imm", (SLEImm GPR32Opnd:$rs,
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GPR32Opnd:$rs,
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simm32:$imm), 0>,
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GPR_32;
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def SLEU : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
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(ins GPR32Opnd:$rs, GPR32Opnd:$rt),
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"sleu\t$rd, $rs, $rt">, ISA_MIPS1;
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def : MipsInstAlias<"sleu $rs, $rt",
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(SLEU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt), 0>,
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ISA_MIPS1;
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def SLEUImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
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(ins GPR32Opnd:$rs, uimm32_coerced:$imm),
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"sleu\t$rd, $rs, $imm">, GPR_32;
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def : MipsInstAlias<"sleu $rs, $imm", (SLEUImm GPR32Opnd:$rs,
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GPR32Opnd:$rs,
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uimm32_coerced:$imm), 0>,
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GPR_32;
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def : MipsInstAlias<
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"not $rt, $rs",
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(NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, ISA_MIPS1;
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31
test/MC/Mips/macro-sle.s
Normal file
31
test/MC/Mips/macro-sle.s
Normal file
@ -0,0 +1,31 @@
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# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips1 < %s | FileCheck %s
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# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s | FileCheck %s
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sle $4, $5
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# CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
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# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
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sle $4, $5, $6
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# CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
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# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
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sle $4, $5, 16
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# CHECK: addiu $4, $zero, 16 # encoding: [0x24,0x04,0x00,0x10]
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# CHECK: slt $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2a]
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# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
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sleu $4, $5
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# CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
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# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
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sleu $4, $5, $6
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# CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
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# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
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sleu $4, $5, 16
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# CHECK: addiu $4, $zero, 16 # encoding: [0x24,0x04,0x00,0x10]
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# CHECK: sltu $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2b]
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# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
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sle $4, 16
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# CHECK: addiu $1, $zero, 16 # encoding: [0x24,0x01,0x00,0x10]
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# CHECK: slt $4, $1, $4 # encoding: [0x00,0x24,0x20,0x2a]
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# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
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sleu $4, 16
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# CHECK: addiu $1, $zero, 16 # encoding: [0x24,0x01,0x00,0x10]
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# CHECK: sltu $4, $1, $4 # encoding: [0x00,0x24,0x20,0x2b]
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# CHECK: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
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29
test/MC/Mips/macro-sle64.s
Normal file
29
test/MC/Mips/macro-sle64.s
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@ -0,0 +1,29 @@
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# RUN: not llvm-mc -arch=mips -mcpu=mips1 < %s 2>&1 \
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# RUN: | FileCheck --check-prefix=MIPS32 %s
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# RUN: llvm-mc -arch=mips -show-encoding -mcpu=mips64 < %s \
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# RUN: | FileCheck --check-prefix=MIPS64 %s
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sle $4, $5, 0x100000000
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# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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# MIPS64: ori $4, $zero, 32768 # encoding: [0x34,0x04,0x80,0x00]
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# MIPS64: dsll $4, $4, 17 # encoding: [0x00,0x04,0x24,0x78]
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# MIPS64: slt $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2a]
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# MIPS64: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
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sleu $4, $5, 0x100000000
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# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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# MIPS64: ori $4, $zero, 32768 # encoding: [0x34,0x04,0x80,0x00]
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# MIPS64: dsll $4, $4, 17 # encoding: [0x00,0x04,0x24,0x78]
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# MIPS64: sltu $4, $4, $5 # encoding: [0x00,0x85,0x20,0x2b]
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# MIPS64: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
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sle $4, 0x100000000
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# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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# MIPS64: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00]
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# MIPS64: dsll $1, $1, 17 # encoding: [0x00,0x01,0x0c,0x78]
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# MIPS64: slt $4, $1, $4 # encoding: [0x00,0x24,0x20,0x2a]
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# MIPS64: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
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sleu $4, 0x100000000
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# MIPS32: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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# MIPS64: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00]
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# MIPS64: dsll $1, $1, 17 # encoding: [0x00,0x01,0x0c,0x78]
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# MIPS64: sltu $4, $1, $4 # encoding: [0x00,0x24,0x20,0x2b]
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# MIPS64: xori $4, $4, 1 # encoding: [0x38,0x84,0x00,0x01]
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