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https://github.com/RPCS3/llvm-mirror.git
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[MachineSink] Add a loop sink limit
To make sure compile-times don't regress, add an option to restrict the number of instructions considered for sinking as alias analysis can be expensive and for the same reason also skip large blocks. Differential Revision: https://reviews.llvm.org/D96485
This commit is contained in:
Sjoerd Meijer
parent
f638cb4edc
commit
86d0604744
@ -97,6 +97,11 @@ SinkInstsIntoLoop("sink-insts-to-avoid-spills",
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"register spills"),
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cl::init(false), cl::Hidden);
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static cl::opt<unsigned> SinkIntoLoopLimit(
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"machine-sink-loop-limit",
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cl::desc("The maximum number of instructions considered for loop sinking."),
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cl::init(50), cl::Hidden);
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STATISTIC(NumSunk, "Number of machine instructions sunk");
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STATISTIC(NumLoopSunk, "Number of machine instructions sunk into a loop");
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STATISTIC(NumSplit, "Number of critical edges split");
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@ -468,7 +473,15 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
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// Walk the candidates in reverse order so that we start with the use
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// of a def-use chain, if there is any.
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// TODO: Sort the candidates using a cost-model.
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unsigned i = 0;
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for (auto It = Candidates.rbegin(); It != Candidates.rend(); ++It) {
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if (i++ == SinkIntoLoopLimit) {
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LLVM_DEBUG(dbgs() << "LoopSink: Limit reached of instructions to "
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"be analysed.");
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break;
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}
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MachineInstr *I = *It;
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if (!SinkIntoLoop(L, *I))
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break;
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@ -1243,6 +1256,10 @@ bool MachineSinking::SinkIntoLoop(MachineLoop *L, MachineInstr &I) {
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LLVM_DEBUG(dbgs() << "LoopSink: Not sinking, sink block is the preheader\n");
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return false;
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}
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if (SinkBlock->size() > SinkLoadInstsPerBlockThreshold) {
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LLVM_DEBUG(dbgs() << "LoopSink: Not Sinking, block too large to analyse.\n");
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return false;
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}
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LLVM_DEBUG(dbgs() << "LoopSink: Sinking instruction!\n");
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SinkBlock->splice(SinkBlock->getFirstNonPHI(), Preheader, I);
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178
test/CodeGen/AArch64/loop-sink-limit.mir
Normal file
178
test/CodeGen/AArch64/loop-sink-limit.mir
Normal file
@ -0,0 +1,178 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=machine-sink -sink-insts-to-avoid-spills \
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# RUN: -machine-sink-loop-limit=1 -verify-machineinstrs %s -o - 2>&1 | \
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# RUN: FileCheck %s --check-prefix=SINK1
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#
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# RUN: llc -mtriple aarch64 -run-pass=machine-sink -sink-insts-to-avoid-spills \
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# RUN: -machine-sink-loop-limit=2 -verify-machineinstrs %s -o - 2>&1 | \
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# RUN: FileCheck %s --check-prefix=SINK2
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64"
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@A = external dso_local global [100 x i32], align 4
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%struct.A = type { i32, i32, i32, i32, i32, i32 }
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define i32 @do_sink_use_is_not_a_copy(i32 %n) {
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entry:
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%cmp63 = icmp sgt i32 %n, 0
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br i1 %cmp63, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader: ; preds = %entry
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%0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
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br label %for.body
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for.cond.cleanup: ; preds = %for.body, %entry
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%sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
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ret i32 %sum.0.lcssa
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for.body: ; preds = %for.body, %for.body.preheader
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%lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
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%sum.065 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
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%div = sdiv i32 %sum.065, %0
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%lsr.iv.next = add i32 %lsr.iv, -1
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%exitcond.not = icmp eq i32 %lsr.iv.next, 0
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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}
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...
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---
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name: do_sink_use_is_not_a_copy
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers:
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- { id: 0, class: gpr32, preferred-register: '' }
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- { id: 1, class: gpr32all, preferred-register: '' }
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- { id: 2, class: gpr32sp, preferred-register: '' }
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- { id: 3, class: gpr32, preferred-register: '' }
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- { id: 4, class: gpr32all, preferred-register: '' }
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- { id: 5, class: gpr32all, preferred-register: '' }
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- { id: 6, class: gpr32common, preferred-register: '' }
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- { id: 7, class: gpr32, preferred-register: '' }
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- { id: 8, class: gpr64common, preferred-register: '' }
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- { id: 9, class: gpr32, preferred-register: '' }
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- { id: 10, class: gpr32, preferred-register: '' }
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- { id: 11, class: gpr32, preferred-register: '' }
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liveins:
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- { reg: '$w0', virtual-reg: '%6' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; SINK1-LABEL: name: do_sink_use_is_not_a_copy
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; SINK1: bb.0.entry:
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; SINK1: successors: %bb.1(0x50000000), %bb.2(0x30000000)
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; SINK1: liveins: $w0
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; SINK1: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
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; SINK1: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
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; SINK1: Bcc 11, %bb.2, implicit $nzcv
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; SINK1: B %bb.1
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; SINK1: bb.1.for.body.preheader:
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; SINK1: successors: %bb.3(0x80000000)
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; SINK1: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @A
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; SINK1: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui killed [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load 4 from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
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; SINK1: B %bb.3
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; SINK1: bb.2.for.cond.cleanup:
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; SINK1: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %4, %bb.3
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; SINK1: $w0 = COPY [[PHI]]
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; SINK1: RET_ReallyLR implicit $w0
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; SINK1: bb.3.for.body:
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; SINK1: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
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; SINK1: [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %5, %bb.3
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; SINK1: [[PHI2:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %4, %bb.3
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; SINK1: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI2]], [[LDRWui]]
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; SINK1: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
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; SINK1: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def $nzcv
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; SINK1: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
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; SINK1: Bcc 0, %bb.2, implicit $nzcv
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; SINK1: B %bb.3
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; SINK2-LABEL: name: do_sink_use_is_not_a_copy
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; SINK2: bb.0.entry:
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; SINK2: successors: %bb.1(0x50000000), %bb.2(0x30000000)
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; SINK2: liveins: $w0
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; SINK2: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
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; SINK2: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
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; SINK2: Bcc 11, %bb.2, implicit $nzcv
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; SINK2: B %bb.1
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; SINK2: bb.1.for.body.preheader:
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; SINK2: successors: %bb.3(0x80000000)
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; SINK2: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @A
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; SINK2: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui killed [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load 4 from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
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; SINK2: B %bb.3
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; SINK2: bb.2.for.cond.cleanup:
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; SINK2: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %4, %bb.3
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; SINK2: $w0 = COPY [[PHI]]
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; SINK2: RET_ReallyLR implicit $w0
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; SINK2: bb.3.for.body:
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; SINK2: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
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; SINK2: [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %5, %bb.3
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; SINK2: [[PHI2:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %4, %bb.3
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; SINK2: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI2]], [[LDRWui]]
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; SINK2: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
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; SINK2: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def $nzcv
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; SINK2: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
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; SINK2: Bcc 0, %bb.2, implicit $nzcv
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; SINK2: B %bb.3
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bb.0.entry:
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successors: %bb.1(0x50000000), %bb.2(0x30000000)
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liveins: $w0
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%6:gpr32common = COPY $w0
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%7:gpr32 = SUBSWri %6, 1, 0, implicit-def $nzcv
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Bcc 11, %bb.2, implicit $nzcv
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B %bb.1
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bb.1.for.body.preheader:
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successors: %bb.3(0x80000000)
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%8:gpr64common = ADRP target-flags(aarch64-page) @A
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%9:gpr32 = LDRWui killed %8, target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load 4 from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
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B %bb.3
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bb.2.for.cond.cleanup:
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%1:gpr32all = PHI %6, %bb.0, %4, %bb.3
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$w0 = COPY %1
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RET_ReallyLR implicit $w0
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bb.3.for.body:
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successors: %bb.2(0x04000000), %bb.3(0x7c000000)
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%2:gpr32sp = PHI %6, %bb.1, %5, %bb.3
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%3:gpr32 = PHI %6, %bb.1, %4, %bb.3
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%10:gpr32 = SDIVWr %3, %9
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%4:gpr32all = COPY %10
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%11:gpr32 = SUBSWri %2, 1, 0, implicit-def $nzcv
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%5:gpr32all = COPY %11
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Bcc 0, %bb.2, implicit $nzcv
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B %bb.3
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...
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