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[PowerPC][AIX] Spill/restore the callee-saved condition register bits.
Extends the existing support for spilling and restoring the condition register to the linkage area for 32-bit targets, and enables for AIX. Differential Revision: https://reviews.llvm.org/D74349
This commit is contained in:
Sean Fertile
parent
417ce65d08
commit
876805ea19
@ -79,9 +79,8 @@ static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) {
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: STI.getTargetMachine().isPositionIndependent() ? -12U : -8U;
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}
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static unsigned computeCRSaveOffset() {
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// The condition register save offset needs to be updated for AIX PPC32.
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return 8;
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static unsigned computeCRSaveOffset(const PPCSubtarget &STI) {
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return (STI.isAIXABI() && !STI.isPPC64()) ? 4 : 8;
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}
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PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
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@ -92,7 +91,7 @@ PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
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FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),
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LinkageSize(computeLinkageSize(Subtarget)),
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BasePointerSaveOffset(computeBasePointerSaveOffset(Subtarget)),
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CRSaveOffset(computeCRSaveOffset()) {}
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CRSaveOffset(computeCRSaveOffset(Subtarget)) {}
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// With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
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const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
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@ -741,7 +740,8 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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MachineModuleInfo &MMI = MF.getMMI();
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const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
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DebugLoc dl;
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bool needsCFI = MF.needsFrameMoves();
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// AIX assembler does not support cfi directives.
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const bool needsCFI = MF.needsFrameMoves() && !Subtarget.isAIXABI();
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// Get processor type.
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bool isPPC64 = Subtarget.isPPC64();
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@ -812,6 +812,9 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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: PPC::SUBFC);
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const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
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: PPC::SUBFIC);
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const MCInstrDesc &MoveFromCondRegInst = TII.get(isPPC64 ? PPC::MFCR8
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: PPC::MFCR);
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const MCInstrDesc &StoreWordInst = TII.get(isPPC64 ? PPC::STW8 : PPC::STW);
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// Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
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// LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
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@ -873,12 +876,6 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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// indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
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bool isLargeFrame = !isInt<16>(NegFrameSize);
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assert((isPPC64 || !MustSaveCR) &&
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"Prologue CR saving supported only in 64-bit mode");
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if (MustSaveCR && isAIXABI)
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report_fatal_error("Prologue CR saving is unimplemented on AIX.");
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// Check if we can move the stack update instruction (stdu) down the prologue
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// past the callee saves. Hopefully this will avoid the situation where the
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// saves are waiting for the update on the store with update to complete.
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@ -918,49 +915,42 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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}
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}
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// Where in the prologue we move the CR fields depends on how many scratch
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// registers we have, and if we need to save the link register or not. This
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// lambda is to avoid duplicating the logic in 2 places.
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auto BuildMoveFromCR = [&]() {
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if (isELFv2ABI && MustSaveCRs.size() == 1) {
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// In the ELFv2 ABI, we are not required to save all CR fields.
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// If only one CR field is clobbered, it is more efficient to use
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// mfocrf to selectively save just that field, because mfocrf has short
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// latency compares to mfcr.
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assert(isPPC64 && "V2 ABI is 64-bit only.");
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, dl, TII.get(PPC::MFOCRF8), TempReg);
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MIB.addReg(MustSaveCRs[0], RegState::Kill);
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} else {
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, dl, MoveFromCondRegInst, TempReg);
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for (unsigned CRfield : MustSaveCRs)
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MIB.addReg(CRfield, RegState::ImplicitKill);
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}
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};
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// If we need to spill the CR and the LR but we don't have two separate
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// registers available, we must spill them one at a time
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if (MustSaveCR && SingleScratchReg && MustSaveLR) {
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// In the ELFv2 ABI, we are not required to save all CR fields.
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// If only one or two CR fields are clobbered, it is more efficient to use
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// mfocrf to selectively save just those fields, because mfocrf has short
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// latency compares to mfcr.
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unsigned MfcrOpcode = PPC::MFCR8;
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unsigned CrState = RegState::ImplicitKill;
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if (isELFv2ABI && MustSaveCRs.size() == 1) {
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MfcrOpcode = PPC::MFOCRF8;
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CrState = RegState::Kill;
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}
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
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for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
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MIB.addReg(MustSaveCRs[i], CrState);
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
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BuildMoveFromCR();
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BuildMI(MBB, MBBI, dl, StoreWordInst)
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.addReg(TempReg, getKillRegState(true))
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.addImm(getCRSaveOffset())
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.addImm(CRSaveOffset)
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.addReg(SPReg);
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}
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if (MustSaveLR)
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BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
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if (MustSaveCR &&
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!(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
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// In the ELFv2 ABI, we are not required to save all CR fields.
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// If only one or two CR fields are clobbered, it is more efficient to use
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// mfocrf to selectively save just those fields, because mfocrf has short
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// latency compares to mfcr.
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unsigned MfcrOpcode = PPC::MFCR8;
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unsigned CrState = RegState::ImplicitKill;
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if (isELFv2ABI && MustSaveCRs.size() == 1) {
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MfcrOpcode = PPC::MFOCRF8;
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CrState = RegState::Kill;
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}
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
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for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
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MIB.addReg(MustSaveCRs[i], CrState);
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}
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if (MustSaveCR && !(SingleScratchReg && MustSaveLR))
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BuildMoveFromCR();
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if (HasRedZone) {
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if (HasFP)
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@ -987,11 +977,11 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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.addReg(SPReg);
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if (MustSaveCR &&
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!(SingleScratchReg && MustSaveLR)) { // will only occur for PPC64
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!(SingleScratchReg && MustSaveLR)) {
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assert(HasRedZone && "A red zone is always available on PPC64");
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BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
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BuildMI(MBB, MBBI, dl, StoreWordInst)
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.addReg(TempReg, getKillRegState(true))
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.addImm(getCRSaveOffset())
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.addImm(CRSaveOffset)
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.addReg(SPReg);
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}
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@ -1295,7 +1285,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF,
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// actually saved gets its own CFI record.
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unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
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unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
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nullptr, MRI->getDwarfRegNum(CRReg, true), getCRSaveOffset()));
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nullptr, MRI->getDwarfRegNum(CRReg, true), CRSaveOffset));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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continue;
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@ -1376,7 +1366,10 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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: PPC::ADDI );
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const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
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: PPC::ADD4 );
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const MCInstrDesc& LoadWordInst = TII.get( isPPC64 ? PPC::LWZ8
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: PPC::LWZ);
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const MCInstrDesc& MoveToCRInst = TII.get( isPPC64 ? PPC::MTOCRF8
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: PPC::MTOCRF);
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int LROffset = getReturnSaveOffset();
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int FPOffset = 0;
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@ -1551,20 +1544,17 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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// value (although not the base register). Make sure it is not overwritten
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// too early.
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assert((isPPC64 || !MustSaveCR) &&
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"Epilogue CR restoring supported only in 64-bit mode");
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// If we need to restore both the LR and the CR and we only have one
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// available scratch register, we must do them one at a time.
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if (MustSaveCR && SingleScratchReg && MustSaveLR) {
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// Here TempReg == ScratchReg, and in the absence of red zone ScratchReg
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// is live here.
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assert(HasRedZone && "Expecting red zone");
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BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
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.addImm(getCRSaveOffset())
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BuildMI(MBB, MBBI, dl, LoadWordInst, TempReg)
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.addImm(CRSaveOffset)
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.addReg(SPReg);
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for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
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BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
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BuildMI(MBB, MBBI, dl, MoveToCRInst, MustSaveCRs[i])
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.addReg(TempReg, getKillRegState(i == e-1));
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}
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@ -1581,11 +1571,9 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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}
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if (MustSaveCR && !(SingleScratchReg && MustSaveLR)) {
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// This will only occur for PPC64.
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assert(isPPC64 && "Expecting 64-bit mode");
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assert(RBReg == SPReg && "Should be using SP as a base register");
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BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
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.addImm(getCRSaveOffset())
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BuildMI(MBB, MBBI, dl, LoadWordInst, TempReg)
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.addImm(CRSaveOffset)
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.addReg(RBReg);
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}
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@ -1640,9 +1628,9 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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}
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if (MustSaveCR &&
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!(SingleScratchReg && MustSaveLR)) // will only occur for PPC64
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!(SingleScratchReg && MustSaveLR))
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for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
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BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
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BuildMI(MBB, MBBI, dl, MoveToCRInst, MustSaveCRs[i])
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.addReg(TempReg, getKillRegState(i == e-1));
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if (MustSaveLR)
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@ -1780,17 +1768,17 @@ void PPCFrameLowering::determineCalleeSaves(MachineFunction &MF,
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MFI.CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
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}
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// For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
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// function uses CR 2, 3, or 4. For 64-bit SVR4 we create a FixedStack
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// Allocate the nonvolatile CR spill slot iff the function uses CR 2, 3, or 4.
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// For 64-bit SVR4, and all flavors of AIX we create a FixedStack
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// object at the offset of the CR-save slot in the linkage area. The actual
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// save and restore of the condition register will be created as part of the
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// prologue and epilogue insertion, but the FixedStack object is needed to
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// keep the CalleSavedInfo valid.
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if (Subtarget.isSVR4ABI() &&
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(SavedRegs.test(PPC::CR2) || SavedRegs.test(PPC::CR3) ||
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if ((SavedRegs.test(PPC::CR2) || SavedRegs.test(PPC::CR3) ||
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SavedRegs.test(PPC::CR4))) {
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const uint64_t SpillSize = 4; // Condition register is always 4 bytes.
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const int64_t SpillOffset = Subtarget.isPPC64() ? 8 : -4;
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const int64_t SpillOffset =
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Subtarget.isPPC64() ? 8 : Subtarget.isAIXABI() ? 4 : -4;
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int FrameIdx =
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MFI.CreateFixedObject(SpillSize, SpillOffset,
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/* IsImmutable */ true, /* IsAliased */ false);
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@ -2141,11 +2129,6 @@ bool PPCFrameLowering::spillCalleeSavedRegisters(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
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// Currently, this function only handles SVR4 32- and 64-bit ABIs.
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// Return false otherwise to maintain pre-existing behavior.
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if (!Subtarget.isSVR4ABI())
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return false;
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MachineFunction *MF = MBB.getParent();
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const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
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PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>();
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@ -2185,7 +2168,7 @@ bool PPCFrameLowering::spillCalleeSavedRegisters(
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// Insert the spill to the stack frame.
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if (IsCRField) {
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PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
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if (Subtarget.isPPC64()) {
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if (!Subtarget.is32BitELFABI()) {
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// The actual spill will happen at the start of the prologue.
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FuncInfo->addMustSaveCR(Reg);
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} else {
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@ -2305,12 +2288,6 @@ PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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// Currently, this function only handles SVR4 32- and 64-bit ABIs.
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// Return false otherwise to maintain pre-existing behavior.
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if (!Subtarget.isSVR4ABI())
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return false;
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MachineFunction *MF = MBB.getParent();
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const PPCInstrInfo &TII = *Subtarget.getInstrInfo();
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PPCFunctionInfo *FI = MF->getInfo<PPCFunctionInfo>();
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@ -2356,7 +2333,7 @@ PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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CR4Spilled = true;
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continue;
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} else {
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// When we first encounter a non-CR register after seeing at
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// On 32-bit ELF when we first encounter a non-CR register after seeing at
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// least one CR register, restore all spilled CRs together.
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if (CR2Spilled || CR3Spilled || CR4Spilled) {
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bool is31 = needsFP(*MF);
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@ -153,10 +153,6 @@ public:
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/// base pointer.
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unsigned getBasePointerSaveOffset() const;
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/// getCRSaveOffset - Return the previous frame offset to save the
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/// CR register.
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unsigned getCRSaveOffset() const { return CRSaveOffset; }
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/// getLinkageSize - Return the size of the PowerPC ABI linkage area.
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///
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unsigned getLinkageSize() const { return LinkageSize; }
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@ -926,14 +926,15 @@ void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II,
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bool PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
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unsigned Reg, int &FrameIdx) const {
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const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
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// For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
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// ABI, return true to prevent allocating an additional frame slot.
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// For 64-bit, the CR save area is in the linkage area at SP+8; but we have
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// created a FrameIndex to that spill slot to keep the CalleSaveInfos valid.
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// For 32-bit, we have previously created the stack slot if needed, so return
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// its FrameIdx.
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if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
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// For the nonvolatile condition registers (CR2, CR3, CR4) return true to
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// prevent allocating an additional frame slot.
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// For 64-bit ELF and AIX, the CR save area is in the linkage area at SP+8,
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// for 32-bit AIX the CR save area is in the linkage area at SP+4.
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// We have created a FrameIndex to that spill slot to keep the CalleSaveInfos
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// valid.
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// For 32-bit ELF, we have previously created the stack slot if needed, so
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// return its FrameIdx.
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if (PPC::CR2 <= Reg && Reg <= PPC::CR4) {
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FrameIdx = MF.getInfo<PPCFunctionInfo>()->getCRSpillFrameIndex();
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return true;
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}
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81
test/CodeGen/PowerPC/aix-crspill.ll
Normal file
81
test/CodeGen/PowerPC/aix-crspill.ll
Normal file
@ -0,0 +1,81 @@
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; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -mcpu=pwr4 --mattr=-altivec \
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; RUN: --verify-machineinstrs < %s | FileCheck --check-prefix=64BIT %s
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; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -mcpu=pwr4 --mattr=-altivec \
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; RUN: --verify-machineinstrs < %s | FileCheck --check-prefix=32BIT %s
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define dso_local signext i32 @killOne(i32 signext %i) {
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entry:
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tail call void asm sideeffect "# Clobber CR", "~{cr4}"()
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%call = call signext i32 @do_something(i32 %i)
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ret i32 %call
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}
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define dso_local signext i32 @killAll(i32 signext %i) {
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entry:
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tail call void asm sideeffect "# Clobber CR", "~{cr0},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}" ()
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%call = call signext i32 @do_something(i32 %i)
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ret i32 %call
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}
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declare signext i32 @do_something(i32 signext)
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; 64BIT-LABEL: .killOne:
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; 64BIT: mflr 0
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; 64BIT-NEXT: std 0, 16(1)
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; 64BIT-NEXT: mfcr 12
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; 64BIT-NEXT: stw 12, 8(1)
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; 64BIT: stdu 1, -112(1)
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; 64BIT: # Clobber CR
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; 64BIT: bl .do_something
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; 64BIT: addi 1, 1, 112
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; 64BIT-NEXT: ld 0, 16(1)
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; 64BIT-NEXT: lwz 12, 8(1)
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; 64BIT-NEXT: mtlr 0
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; 64BIT-NEXT: mtocrf 8, 12
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; 64BIT: blr
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; 32BIT-LABEL: .killOne:
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; 32BIT: mflr 0
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; 32BIT-NEXT: stw 0, 8(1)
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; 32BIT-NEXT: mfcr 12
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; 32BIT-NEXT: stw 12, 4(1)
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; 32BIT: stwu 1, -64(1)
|
||||
|
||||
; 32BIT: # Clobber CR
|
||||
; 32BIT: bl .do_something
|
||||
|
||||
; 32BIT: addi 1, 1, 64
|
||||
; 32BIT-NEXT: lwz 0, 8(1)
|
||||
; 32BIT-NEXT: lwz 12, 4(1)
|
||||
; 32BIT-NEXT: mtlr 0
|
||||
; 32BIT-NEXT: mtocrf 8, 12
|
||||
; 32BIT: blr
|
||||
|
||||
|
||||
; 64BIT-LABEL: .killAll:
|
||||
|
||||
; 64BIT: addi 1, 1, 112
|
||||
; 64BIT-NEXT: ld 0, 16(1)
|
||||
; 64BIT-NEXT: lwz 12, 8(1)
|
||||
; 64BIT-NEXT: mtlr 0
|
||||
; 64BIT-NEXT: mtocrf 32, 12
|
||||
; 64BIT-NEXT: mtocrf 16, 12
|
||||
; 64BIT-NEXT: mtocrf 8, 12
|
||||
; 64BIT-NEXT: blr
|
||||
|
||||
|
||||
; 32BIT-LABEL: .killAll:
|
||||
|
||||
; 32BIT: addi 1, 1, 64
|
||||
; 32BIT-NEXT: lwz 0, 8(1)
|
||||
; 32BIT-NEXT: lwz 12, 4(1)
|
||||
; 32BIT-NEXT: mtlr 0
|
||||
; 32BIT-NEXT: mtocrf 32, 12
|
||||
; 32BIT-NEXT: mtocrf 16, 12
|
||||
; 32BIT-NEXT: mtocrf 8, 12
|
||||
; 32BIT-NEXT: blr
|
||||
66
test/CodeGen/PowerPC/aix32-crsave.mir
Normal file
66
test/CodeGen/PowerPC/aix32-crsave.mir
Normal file
@ -0,0 +1,66 @@
|
||||
# RUN: llc -mtriple powerpc-unknown-aix-xcoff -x mir -mcpu=pwr4 \
|
||||
# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
|
||||
# RUN: FileCheck %s --check-prefixes=CHECK
|
||||
|
||||
---
|
||||
name: CRMultiSave
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$r3', virtual-reg: '' }
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $r3
|
||||
renamable $r29 = ANDI_rec killed renamable $r3, 1, implicit-def dead $cr0, implicit-def $cr0gt
|
||||
renamable $cr2lt = COPY $cr0gt
|
||||
renamable $cr4lt = COPY $cr0gt
|
||||
renamable $r3 = COPY $r29
|
||||
BLR implicit $lr, implicit $rm, implicit $r3
|
||||
|
||||
; CHECK-LABEL: fixedStack:
|
||||
; CHECK: - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
|
||||
; CHECK-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '$cr4',
|
||||
; CHECK-NEXT: callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
|
||||
; CHECK-NEXT: debug-info-location: '' }
|
||||
; CHECK-LABEL: stack:
|
||||
|
||||
; CHECK: bb.0.entry:
|
||||
; CHECK-NEXT: liveins: $r3, $r29, $cr2, $cr4
|
||||
|
||||
; CHECK: $r12 = MFCR implicit killed $cr2, implicit killed $cr4
|
||||
; CHECK-NEXT: STW killed $r12, 4, $r1
|
||||
|
||||
; CHECK: $r12 = LWZ 4, $r1
|
||||
; CHECK-NEXT: $cr2 = MTOCRF $r12
|
||||
; CHECK-NEXT: $cr4 = MTOCRF killed $r12
|
||||
|
||||
...
|
||||
---
|
||||
name: CR3Save
|
||||
alignment: 16
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$r3', virtual-reg: '' }
|
||||
body: |
|
||||
bb.0.entry:
|
||||
liveins: $r3
|
||||
renamable $r14 = ANDI_rec killed renamable $r3, 1, implicit-def dead $cr0, implicit-def $cr0gt
|
||||
renamable $cr3lt = COPY $cr0gt
|
||||
renamable $r3 = COPY $r14
|
||||
BLR implicit $lr, implicit $rm, implicit $r3
|
||||
|
||||
; CHECK-LABEL: fixedStack:
|
||||
; CHECK: - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
|
||||
; CHECK-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '$cr3',
|
||||
; CHECK-NEXT: callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
|
||||
; CHECK-NEXT: debug-info-location: '' }
|
||||
; CHECK-LABEL: stack:
|
||||
|
||||
; CHECK: bb.0.entry:
|
||||
; CHECK-NEXT: liveins: $r3, $r14, $cr3
|
||||
|
||||
; CHECK: $r12 = MFCR implicit killed $cr3
|
||||
; CHECK-NEXT: STW killed $r12, 4, $r1
|
||||
|
||||
; CHECK: $r12 = LWZ 4, $r1
|
||||
; CHECK-NEXT: $cr3 = MTOCRF killed $r12
|
||||
136
test/CodeGen/PowerPC/alloca-crspill.ll
Normal file
136
test/CodeGen/PowerPC/alloca-crspill.ll
Normal file
@ -0,0 +1,136 @@
|
||||
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu --verify-machineinstrs \
|
||||
; RUN: -stop-after=prologepilog < %s | FileCheck \
|
||||
; RUN: --check-prefixes=CHECK,CHECK64,ELFV2 %s
|
||||
|
||||
; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -mcpu=pwr4 \
|
||||
; RUN: --verify-machineinstrs --mattr=-altivec -stop-after=prologepilog < %s | \
|
||||
; RUN: FileCheck --check-prefixes=CHECK,CHECK64,V1ANDAIX %s
|
||||
|
||||
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 --verify-machineinstrs \
|
||||
; RUN: -stop-after=prologepilog < %s | FileCheck \
|
||||
; RUN: --check-prefixes=CHECK,CHECK64,V1ANDAIX %s
|
||||
|
||||
; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -mcpu=pwr4 \
|
||||
; RUN: --verify-machineinstrs --mattr=-altivec -stop-after=prologepilog < %s | \
|
||||
; RUN: FileCheck --check-prefixes=CHECK,CHECK32 %s
|
||||
|
||||
define dso_local signext i32 @test(i32 signext %n) {
|
||||
entry:
|
||||
%conv = sext i32 %n to i64
|
||||
%0 = alloca double, i64 %conv, align 16
|
||||
tail call void asm sideeffect "", "~{cr2}"()
|
||||
%call = call signext i32 @do_something(double* nonnull %0)
|
||||
ret i32 %call
|
||||
}
|
||||
|
||||
declare signext i32 @do_something(double*)
|
||||
|
||||
; CHECK: name: test
|
||||
; CHECK: alignment: 16
|
||||
; CHECK: liveins:
|
||||
; CHECK64: - { reg: '$x3', virtual-reg: '' }
|
||||
; CHECK32: - { reg: '$r3', virtual-reg: '' }
|
||||
|
||||
; ELFV2: stackSize: 48
|
||||
; V1ANDAIX: stackSize: 128
|
||||
; CHECK32: stackSize: 80
|
||||
|
||||
; ELFV2: maxCallFrameSize: 32
|
||||
; V1ANDAIX: maxCallFrameSize: 112
|
||||
; CHECK32: maxCallFrameSize: 64
|
||||
|
||||
; CHECK64: fixedStack:
|
||||
; CHECK64-NEXT: - { id: 0, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
|
||||
; CHECK64-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '$cr2',
|
||||
; CHECK64-NEXT: callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
|
||||
; CHECK64-NEXT: debug-info-location: '' }
|
||||
; CHECK64-NEXT: - { id: 1, type: default, offset: -8, size: 8, alignment: 8, stack-id: default,
|
||||
; CHECK64-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
|
||||
; CHECK64-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
|
||||
; CHECK64-NEXT: stack:
|
||||
; CHECK64-NEXT: - { id: 0, name: '<unnamed alloca>', type: variable-sized, offset: -8,
|
||||
; CHECK64-NEXT: alignment: 1, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
|
||||
; CHECK64-NEXT: local-offset: 0, debug-info-variable: '', debug-info-expression: '',
|
||||
; CHECK64-NEXT: debug-info-location: '' }
|
||||
; CHECK64-NEXT: - { id: 1, name: '', type: default, offset: -16, size: 8, alignment: 8,
|
||||
; CHECK64-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
|
||||
; CHECK64-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
|
||||
|
||||
; CHECK32: fixedStack:
|
||||
; CHECK32-NEXT: - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
|
||||
; CHECK32-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '$cr2',
|
||||
; CHECK32-NEXT: callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
|
||||
; CHECK32-NEXT: debug-info-location: '' }
|
||||
; CHECK32-NEXT: - { id: 1, type: default, offset: -4, size: 4, alignment: 4, stack-id: default,
|
||||
; CHECK32-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
|
||||
; CHECK32-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
|
||||
; CHECK32-NEXT: stack:
|
||||
; CHECK32-NEXT: - { id: 0, name: '<unnamed alloca>', type: variable-sized, offset: -4,
|
||||
; CHECK32-NEXT: alignment: 1, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
|
||||
; CHECK32-NEXT: local-offset: 0, debug-info-variable: '', debug-info-expression: '',
|
||||
; CHECK32-NEXT: debug-info-location: '' }
|
||||
; CHECK32-NEXT: - { id: 1, name: '', type: default, offset: -8, size: 4, alignment: 4,
|
||||
; CHECK32-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
|
||||
; CHECK32-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
|
||||
|
||||
; CHECK64: bb.0.entry:
|
||||
; CHECK64-NEXT: liveins: $x3, $cr2
|
||||
|
||||
; Prologue:
|
||||
; CHECK64: $x0 = MFLR8 implicit $lr8
|
||||
; ELFV2-NEXT: $x12 = MFOCRF8 killed $cr2
|
||||
; V1ANDAIX-NEXT: $x12 = MFCR8 implicit killed $cr2
|
||||
; CHECK64-DAG: STD $x31, -8, $x1
|
||||
; CHECK64-DAG: STD killed $x0, 16, $x1
|
||||
; CHECK64-DAG: STW8 killed $x12, 8, $x1
|
||||
|
||||
; ELFV2-NEXT: $x1 = STDU $x1, -48, $x1
|
||||
; V1ANDAIX-NEXT: x1 = STDU $x1, -128, $x1
|
||||
|
||||
; CHECK64: $x31 = OR8 $x1, $x1
|
||||
|
||||
; ELFV2: $[[ORIGSP:x[0-9]+]] = ADDI8 $x31, 48
|
||||
; V1ANDAIX: $[[ORIGSP:x[0-9]+]] = ADDI8 $x31, 128
|
||||
; CHECK64: $x1 = STDUX killed $[[ORIGSP]], $x1, killed $x{{[0-9]}}
|
||||
; CHECK64: INLINEASM {{.*}} early-clobber $cr2
|
||||
; CHECK64: BL8_NOP
|
||||
|
||||
|
||||
; Epilogue:
|
||||
; CHECK64: $x1 = LD 0, $x1
|
||||
; CHECK64-DAG: $x0 = LD 16, $x1
|
||||
; CHECK64-DAG: $x12 = LWZ8 8, $x1
|
||||
; CHECK64-DAG: $x31 = LD -8, $x1
|
||||
; CHECK64: $cr2 = MTOCRF8 killed $x12
|
||||
; CHECK64-NEXT: MTLR8 $x0, implicit-def $lr8
|
||||
; CHECK64-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
|
||||
|
||||
; CHECK32: bb.0.entry:
|
||||
; CHECK32-NEXT: liveins: $r3, $cr2
|
||||
|
||||
; Prologue:
|
||||
; CHECK32: $r0 = MFLR implicit $lr
|
||||
; CHECK32-NEXT: $r12 = MFCR implicit killed $cr2
|
||||
; CHECK32-DAG: STW $r31, -4, $r1
|
||||
; CHECK32-DAG: STW killed $r0, 8, $r1
|
||||
; CHECK32-DAG: STW killed $r12, 4, $r1
|
||||
; CHECK32: $r1 = STWU $r1, -80, $r1
|
||||
|
||||
; CHECK32: $r31 = OR $r1, $r1
|
||||
; CHECK32: $[[ORIGSP:r[0-9]+]] = ADDI $r31, 80
|
||||
; CHECK32: $r1 = STWUX killed $[[ORIGSP]], $r1, killed $r{{[0-9]}}
|
||||
; CHECK32: INLINEASM {{.*}} early-clobber $cr2
|
||||
; CHECK32: BL_NOP
|
||||
|
||||
; Epilogue:
|
||||
; CHECK32: $r1 = LWZ 0, $r1
|
||||
; CHECK32-DAG: $r0 = LWZ 8, $r1
|
||||
; CHECK32-DAG: $r12 = LWZ 4, $r1
|
||||
; CHECK32-DAG: $r31 = LWZ -4, $r1
|
||||
; CHECK32: $cr2 = MTOCRF killed $r12
|
||||
; CHECK32-NEXT: MTLR $r0, implicit-def $lr
|
||||
; CHECK32-NEXT: BLR implicit $lr, implicit $rm, implicit $r3
|
||||
@ -1,66 +0,0 @@
|
||||
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu --verify-machineinstrs \
|
||||
; RUN: -stop-after=prologepilog < %s | FileCheck %s
|
||||
|
||||
define dso_local signext i32 @test(i32 signext %n) {
|
||||
entry:
|
||||
%conv = sext i32 %n to i64
|
||||
%0 = alloca double, i64 %conv, align 16
|
||||
tail call void asm sideeffect "", "~{cr2}"()
|
||||
%call = call signext i32 @do_something(double* nonnull %0)
|
||||
ret i32 %call
|
||||
}
|
||||
|
||||
declare signext i32 @do_something(double*)
|
||||
|
||||
; CHECK: name: test
|
||||
; CHECK: alignment: 16
|
||||
; CHECK: liveins:
|
||||
; CHECK: - { reg: '$x3', virtual-reg: '' }
|
||||
; CHECK: stackSize: 48
|
||||
; CHECK: maxCallFrameSize: 32
|
||||
|
||||
; CHECK: fixedStack:
|
||||
; CHECK-NEXT: - { id: 0, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
|
||||
; CHECK-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '$cr2',
|
||||
; CHECK-NEXT: callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
|
||||
; CHECK-NEXT: debug-info-location: '' }
|
||||
; CHECK-NEXT: - { id: 1, type: default, offset: -8, size: 8, alignment: 8, stack-id: default,
|
||||
; CHECK-NEXT: isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
|
||||
; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
|
||||
; CHECK-NEXT: stack:
|
||||
; CHECK-NEXT: - { id: 0, name: '<unnamed alloca>', type: variable-sized, offset: -8,
|
||||
; CHECK-NEXT: alignment: 1, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
|
||||
; CHECK-NEXT: local-offset: 0, debug-info-variable: '', debug-info-expression: '',
|
||||
; CHECK-NEXT: debug-info-location: '' }
|
||||
; CHECK-NEXT: - { id: 1, name: '', type: default, offset: -16, size: 8, alignment: 8,
|
||||
; CHECK-NEXT: stack-id: default, callee-saved-register: '', callee-saved-restored: true,
|
||||
; CHECK-NEXT: debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
|
||||
|
||||
; CHECK: bb.0.entry:
|
||||
; CHECK-NEXT: liveins: $x3, $cr2
|
||||
|
||||
; Prologue:
|
||||
; CHECK: $x0 = MFLR8 implicit $lr8
|
||||
; CHECK-NEXT: $x12 = MFOCRF8 killed $cr2
|
||||
; CHECK-DAG: STD $x31, -8, $x1
|
||||
; CHECK-DAG: STD killed $x0, 16, $x1
|
||||
; CHECK-DAG: STW8 killed $x12, 8, $x1
|
||||
; CHECK-NEXT: $x1 = STDU $x1, -48, $x1
|
||||
; CHECK: $x31 = OR8 $x1, $x1
|
||||
|
||||
; CHECK: $[[ORIGSP:x[0-9]+]] = ADDI8 $x31, 48
|
||||
; CHECK: $x1 = STDUX killed $[[ORIGSP]], $x1, killed $x{{[0-9]}}
|
||||
; CHECK: INLINEASM {{.*}} early-clobber $cr2
|
||||
; CHECK: BL8_NOP @do_something
|
||||
|
||||
|
||||
; Epilogue:
|
||||
; CHECK: $x1 = LD 0, $x1
|
||||
; CHECK-DAG: $x0 = LD 16, $x1
|
||||
; CHECK-DAG: $x12 = LWZ8 8, $x1
|
||||
; CHECK-DAG: $x31 = LD -8, $x1
|
||||
; CHECK: $cr2 = MTOCRF8 killed $x12
|
||||
; CHECK-NEXT: MTLR8 $x0, implicit-def $lr8
|
||||
; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
|
||||
|
||||
@ -1,10 +1,18 @@
|
||||
# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -x mir -mcpu=pwr8 \
|
||||
# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
|
||||
# RUN: FileCheck %s --check-prefixes=CHECK,PWR8
|
||||
# RUN: FileCheck %s --check-prefixes=CHECK,SAVEONE,ELF
|
||||
|
||||
# RUN: llc -mtriple powerpc64-unknown-linux-gnu -x mir -mcpu=pwr7 \
|
||||
# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
|
||||
# RUN: FileCheck %s --check-prefixes=CHECK,PWR7
|
||||
# RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL,ELF
|
||||
|
||||
|
||||
# RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 \
|
||||
# RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
|
||||
# RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
|
||||
|
||||
# TODO FIXME: We only check the save and restores of the callee saved gpr for
|
||||
# ELF becuase AIX callee saved registers haven't been properly implemented yet.
|
||||
|
||||
---
|
||||
name: CRAllSave
|
||||
@ -21,19 +29,26 @@ body: |
|
||||
renamable $x3 = COPY $x29
|
||||
BLR8 implicit $lr8, implicit $rm, implicit $x3
|
||||
|
||||
; CHECK-LABEL: fixedStack:
|
||||
; ELF: - { id: 1, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
|
||||
; AIX: - { id: 0, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
|
||||
; CHECK: isImmutable: true, isAliased: false, callee-saved-register: '$cr4',
|
||||
; CHECK-NEXT: callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
|
||||
; CHECK-NEXT: debug-info-location: '' }
|
||||
; CHECK-LABEL: stack:
|
||||
|
||||
; Verify the proper live-ins have been added in the prologue.
|
||||
; CHECK: liveins: $x3, $x29, $cr2, $cr4
|
||||
|
||||
; CHECK: $x12 = MFCR8 implicit killed $cr2, implicit killed $cr4
|
||||
; CHECK-DAG: STD killed $x29, -24, $x1 :: (store 8 into %fixed-stack.0)
|
||||
; ELF-DAG: STD killed $x29, -24, $x1 :: (store 8 into %fixed-stack.0)
|
||||
; CHECK-DAG: STW8 killed $x12, 8, $x1
|
||||
|
||||
; CHECK: $x29 = LD -24, $x1 :: (load 8 from %fixed-stack.0)
|
||||
; ELF: $x29 = LD -24, $x1 :: (load 8 from %fixed-stack.0)
|
||||
; CHECK: $x12 = LWZ8 8, $x1
|
||||
; CHECK: $cr2 = MTOCRF8 $x12
|
||||
; CHECK: $cr4 = MTOCRF8 killed $x12
|
||||
|
||||
|
||||
...
|
||||
---
|
||||
name: CR2Save
|
||||
@ -49,17 +64,28 @@ body: |
|
||||
renamable $x3 = COPY $x14
|
||||
BLR8 implicit $lr8, implicit $rm, implicit $x3
|
||||
|
||||
; CHECK: CR2Save
|
||||
; CHECK-LABEL: CR2Save
|
||||
|
||||
; CHECK-LABEL: fixedStack:
|
||||
; ELF: - { id: 1, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
|
||||
; AIX: - { id: 0, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
|
||||
; CHECK: isImmutable: true, isAliased: false, callee-saved-register: '$cr2',
|
||||
; CHECK-NEXT: callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
|
||||
; CHECK-NEXT: debug-info-location: '' }
|
||||
; CHECK-LABEL: stack:
|
||||
|
||||
; Verify the proper live-ins have been added in the prologue.
|
||||
; CHECK: liveins: $x3, $x14, $cr2
|
||||
|
||||
; PWR8: $x12 = MFOCRF8 killed $cr2
|
||||
; PWR7: $x12 = MFCR8 implicit killed $cr2
|
||||
; ELF V2 ABI allows saving only the clobbered cr fields,
|
||||
; whereas the other ABIs do not.
|
||||
; SAVEONE: $x12 = MFOCRF8 killed $cr2
|
||||
; SAVEALL: $x12 = MFCR8 implicit killed $cr2
|
||||
|
||||
; CHECK-DAG: STD killed $x14, -144, $x1 :: (store 8 into %fixed-stack.0, align 16)
|
||||
; ELF-DAG: STD killed $x14, -144, $x1 :: (store 8 into %fixed-stack.0, align 16)
|
||||
; CHECK-DAG: STW8 killed $x12, 8, $x1
|
||||
|
||||
; CHECK: $x14 = LD -144, $x1 :: (load 8 from %fixed-stack.0, align 16)
|
||||
; ELF: $x14 = LD -144, $x1 :: (load 8 from %fixed-stack.0, align 16)
|
||||
; CHECK: $x12 = LWZ8 8, $x1
|
||||
; CHECK: $cr2 = MTOCRF8 killed $x12
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user