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SSE / SSE2 conversion intrinsics.
llvm-svn: 27637
This commit is contained in:
Evan Cheng
parent
f51d58020e
commit
8768f25c80
@ -112,16 +112,11 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse_cvtss2si : GCCBuiltin<"__builtin_ia32_cvtss2si">,
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Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [IntrNoMem]>;
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def int_x86_sse_cvtps2pi : GCCBuiltin<"__builtin_ia32_cvtps2pi">,
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Intrinsic<[llvm_v2i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
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def int_x86_sse_cvttss2si : GCCBuiltin<"__builtin_ia32_cvttss2si">,
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Intrinsic<[llvm_int_ty, llvm_v4f32_ty], [IntrNoMem]>;
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def int_x86_sse_cvttps2pi : GCCBuiltin<"__builtin_ia32_cvttps2pi">,
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Intrinsic<[llvm_v2i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
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def int_x86_sse_cvtsi2ss : GCCBuiltin<"__builtin_ia32_cvtsi2ss">,
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Intrinsic<[llvm_v4f32_ty, llvm_int_ty], [IntrNoMem]>;
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def int_x86_sse_cvtpi2ps : GCCBuiltin<"__builtin_ia32_cvtpi2ps">,
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Intrinsic<[llvm_v4f32_ty, llvm_v2i32_ty], [IntrNoMem]>;
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_int_ty], [IntrNoMem]>;
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}
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// SIMD load ops
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@ -287,6 +282,15 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem]>;
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def int_x86_sse2_cvttsd2si : GCCBuiltin<"__builtin_ia32_cvttsd2si">,
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Intrinsic<[llvm_int_ty, llvm_v2f64_ty], [IntrNoMem]>;
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def int_x86_sse2_cvtsi2sd : GCCBuiltin<"__builtin_ia32_cvtsi2sd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_int_ty], [IntrNoMem]>;
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def int_x86_sse2_cvtsd2ss : GCCBuiltin<"__builtin_ia32_cvtsd2ss">,
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Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
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llvm_v2f64_ty], [IntrNoMem]>;
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def int_x86_sse2_cvtss2sd : GCCBuiltin<"__builtin_ia32_cvtss2sd">,
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Intrinsic<[llvm_v2f64_ty, llvm_v2f64_ty,
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llvm_v4f32_ty], [IntrNoMem]>;
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}
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// SIMD load ops
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@ -14,7 +14,13 @@
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//===----------------------------------------------------------------------===//
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// Instruction templates
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// MMXi8 - MMX instructions with ImmT == Imm8 and TB prefix.
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// MMXI - MMX instructions with TB prefix.
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// MMX2I - MMX / SSE2 instructions with TB and OpSize prefixes.
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// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
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class MMXI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: I<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
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class MMX2I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
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class MMXIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
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: X86Inst<o, F, Imm8, ops, asm>, TB, Requires<[HasMMX]> {
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let Pattern = pattern;
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@ -51,12 +57,28 @@ def MOVQ64mr : I<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
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Requires<[HasMMX]>;
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// Conversion instructions
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def CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
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"cvtpi2ps {$src, $dst|$dst, $src}", []>;
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def CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
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"cvtpi2ps {$src, $dst|$dst, $src}", []>;
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def CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
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"cvtpi2pd {$src, $dst|$dst, $src}", []>;
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def CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
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"cvtpi2pd {$src, $dst|$dst, $src}", []>;
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def CVTTPS2PIrr: I<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src),
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"cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasSSE2]>;
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def CVTTPS2PIrm: I<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
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"cvttps2pi {$src, $dst|$dst, $src}", []>, TB,
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Requires<[HasMMX]>;
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def CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
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"cvtps2pi {$src, $dst|$dst, $src}", []>;
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def CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
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"cvtps2pi {$src, $dst|$dst, $src}", []>;
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def CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
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"cvtpd2pi {$src, $dst|$dst, $src}", []>;
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def CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
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"cvtpd2pi {$src, $dst|$dst, $src}", []>;
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// Shuffle and unpack instructions
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def PSHUFWri : MMXIi8<0x70, MRMSrcReg,
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@ -479,11 +479,6 @@ def Int_MINSDrm : SD_Intrm<0x5D, "minsd {$src2, $dst|$dst, $src2}",
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}
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// Conversion instructions
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def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops R32:$dst, FR32:$src),
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"cvtss2si {$src, $dst|$dst, $src}", []>;
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def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
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"cvtss2si {$src, $dst|$dst, $src}", []>;
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def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
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"cvttss2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (fp_to_sint FR32:$src))]>;
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@ -514,6 +509,7 @@ def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src),
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def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
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"cvtsi2sd {$src, $dst|$dst, $src}",
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[(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
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// SSE2 instructions with XS prefix
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def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
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"cvtss2sd {$src, $dst|$dst, $src}",
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@ -524,7 +520,23 @@ def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
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[(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS,
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Requires<[HasSSE2]>;
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// Aliases to match intrinsics which expect XMM operand(s).
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// Match intrinsics which expect XMM operand(s).
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def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
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"cvtss2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
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def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
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"cvtss2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse_cvtss2si
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(loadv4f32 addr:$src)))]>;
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// Aliases for intrinsics
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def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
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"cvttss2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse_cvttss2si VR128:$src))]>;
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def Int_CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
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"cvttss2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse_cvttss2si
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(loadv4f32 addr:$src)))]>;
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def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
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"cvttsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>;
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@ -533,13 +545,18 @@ def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f128mem:$src),
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[(set R32:$dst, (int_x86_sse2_cvttsd2si
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(loadv2f64 addr:$src)))]>;
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def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
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"cvtsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
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def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src),
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"cvtsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse2_cvtsd2si
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(loadv2f64 addr:$src)))]>;
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let isTwoAddress = 1 in {
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def Int_CVTSI2SSrr: SSI<0x2A, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, R32:$src2),
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"cvtsi2ss {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
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R32:$src2))]>;
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def Int_CVTSI2SSrm: SSI<0x2A, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, i32mem:$src2),
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"cvtsi2ss {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
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(loadi32 addr:$src2)))]>;
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}
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// Comparison instructions
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let isTwoAddress = 1 in {
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@ -816,16 +833,6 @@ def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
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MOVHLPS_shuffle_mask)))]>;
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}
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// Conversion instructions
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def CVTPI2PSrr : PSI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
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"cvtpi2ps {$src, $dst|$dst, $src}", []>;
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def CVTPI2PSrm : PSI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
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"cvtpi2ps {$src, $dst|$dst, $src}", []>;
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def CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
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"cvtpi2pd {$src, $dst|$dst, $src}", []>;
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def CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
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"cvtpi2pd {$src, $dst|$dst, $src}", []>;
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// SSE2 instructions without OpSize prefix
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def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"cvtdq2ps {$src, $dst|$dst, $src}",
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@ -848,15 +855,6 @@ def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
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(bc_v4i32 (loadv2i64 addr:$src))))]>,
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XS, Requires<[HasSSE2]>;
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def CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
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"cvtps2pi {$src, $dst|$dst, $src}", []>;
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def CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
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"cvtps2pi {$src, $dst|$dst, $src}", []>;
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def CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
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"cvtpd2pi {$src, $dst|$dst, $src}", []>;
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def CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
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"cvtpd2pi {$src, $dst|$dst, $src}", []>;
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def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
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"cvtps2dq {$src, $dst|$dst, $src}",
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[(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
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@ -912,6 +910,52 @@ def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
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[(set VR128:$dst, (int_x86_sse2_cvtpd2ps
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(loadv2f64 addr:$src)))]>;
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def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
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"cvtsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
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def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src),
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"cvtsd2si {$src, $dst|$dst, $src}",
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[(set R32:$dst, (int_x86_sse2_cvtsd2si
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(loadv2f64 addr:$src)))]>;
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// Match intrinsics which expect XMM operand(s).
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// Aliases for intrinsics
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let isTwoAddress = 1 in {
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def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, R32:$src2),
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"cvtsi2sd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
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R32:$src2))]>;
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def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, i32mem:$src2),
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"cvtsi2sd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
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(loadi32 addr:$src2)))]>;
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def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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"cvtsd2ss {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
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VR128:$src2))]>;
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def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f64mem:$src2),
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"cvtsd2ss {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
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(loadv2f64 addr:$src2)))]>;
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def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
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(ops VR128:$dst, VR128:$src1, VR128:$src2),
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"cvtss2sd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
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VR128:$src2))]>, XS,
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Requires<[HasSSE2]>;
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def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
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(ops VR128:$dst, VR128:$src1, f32mem:$src2),
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"cvtss2sd {$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
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(loadv4f32 addr:$src2)))]>, XS,
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Requires<[HasSSE2]>;
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}
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// Arithmetic
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let isTwoAddress = 1 in {
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let isCommutable = 1 in {
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