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[GlobalISel] Fix assertion failures after "GlobalISel: Return APInt from getConstantVRegVal" landed.
APInt binary ops don't promote types but instead assert, which a combine was relying on.
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@ -1570,7 +1570,8 @@ bool CombinerHelper::matchShiftImmedChain(MachineInstr &MI,
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return false;
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// Pass the combined immediate to the apply function.
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MatchInfo.Imm = (MaybeImmVal->Value + MaybeImm2Val->Value).getSExtValue();
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MatchInfo.Imm =
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(MaybeImmVal->Value.getSExtValue() + MaybeImm2Val->Value).getSExtValue();
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MatchInfo.Reg = Base;
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// There is no simple replacement for a saturating unsigned left shift that
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@ -0,0 +1,58 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
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---
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name: shift_immed_chain_mismatch_size_crash
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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body: |
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; CHECK-LABEL: name: shift_immed_chain_mismatch_size_crash
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $x0
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; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
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; CHECK: [[DEF1:%[0-9]+]]:_(s1) = G_IMPLICIT_DEF
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; CHECK: G_BRCOND [[DEF1]](s1), %bb.2
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; CHECK: G_BR %bb.1
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; CHECK: bb.1:
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; CHECK: successors:
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; CHECK: bb.2:
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; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4 from `i32* undef`, align 8)
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; CHECK: [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[C]], [[LOAD]]
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; CHECK: [[MUL1:%[0-9]+]]:_(s32) = nsw G_MUL [[MUL]], [[C1]]
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; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
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; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[MUL1]], [[C2]](s64)
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; CHECK: $w0 = COPY [[SHL]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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bb.1:
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liveins: $x0
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%0:_(p0) = COPY $x0
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%1:_(s1) = G_IMPLICIT_DEF
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%3:_(p0) = G_IMPLICIT_DEF
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%4:_(s32) = G_CONSTANT i32 16
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%6:_(s32) = G_CONSTANT i32 9
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%8:_(s32) = G_CONSTANT i32 2
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%11:_(s64) = G_CONSTANT i64 2
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G_BRCOND %1(s1), %bb.2
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G_BR %bb.3
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bb.2:
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successors:
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bb.3:
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%2:_(s32) = G_LOAD %3(p0) :: (load 4 from `i32* undef`, align 8)
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%5:_(s32) = nsw G_MUL %4, %2
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%7:_(s32) = nsw G_MUL %5, %6
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%9:_(s32) = nsw G_MUL %7, %8
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%10:_(s64) = G_SEXT %9(s32)
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%12:_(s64) = G_MUL %10, %11
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%13:_(s32) = G_TRUNC %12(s64)
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$w0 = COPY %13(s32)
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RET_ReallyLR implicit $w0
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...
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