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[PowerPC] Implement vector shift builtins - llvm portion

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This patch corresponds to review https://reviews.llvm.org/D26095.
Committing on behalf of Tony Jiang.

llvm-svn: 285681
This commit is contained in:
Nemanja Ivanovic 2016-11-01 09:42:32 +00:00
parent 1fe9a11b5d
commit 87dcd90e97
3 changed files with 29 additions and 2 deletions
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2
include/llvm/IR/IntrinsicsPowerPC.td
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@ -622,6 +622,8 @@ def int_ppc_altivec_vsl : PowerPC_Vec_WWW_Intrinsic<"vsl">;
def int_ppc_altivec_vslo : PowerPC_Vec_WWW_Intrinsic<"vslo">;
def int_ppc_altivec_vslb : PowerPC_Vec_BBB_Intrinsic<"vslb">;
def int_ppc_altivec_vslv : PowerPC_Vec_BBB_Intrinsic<"vslv">;
def int_ppc_altivec_vsrv : PowerPC_Vec_BBB_Intrinsic<"vsrv">;
def int_ppc_altivec_vslh : PowerPC_Vec_HHH_Intrinsic<"vslh">;
def int_ppc_altivec_vslw : PowerPC_Vec_WWW_Intrinsic<"vslw">;

6
lib/Target/PowerPC/PPCInstrAltivec.td
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@ -1342,8 +1342,10 @@ def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm", []>;
def VRLDMI : VX1_VT5_VA5_VB5<197, "vrldmi", []>;
// Vector Shift Left/Right
def VSLV : VX1_VT5_VA5_VB5<1860, "vslv", []>;
def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv", []>;
def VSLV : VX1_VT5_VA5_VB5<1860, "vslv",
[(set v16i8 : $vD, (int_ppc_altivec_vslv v16i8 : $vA, v16i8 : $vB))]>;
def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv",
[(set v16i8 : $vD, (int_ppc_altivec_vsrv v16i8 : $vA, v16i8 : $vB))]>;
// Vector Multiply-by-10 (& Write Carry) Unsigned Quadword
def VMUL10UQ : VXForm_BX<513, (outs vrrc:$vD), (ins vrrc:$vA),

23
test/CodeGen/PowerPC/vsx-p9.ll
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@ -167,4 +167,27 @@ entry:
; Function Attrs: nounwind readnone
declare <2 x double> @llvm.ppc.vsx.xviexpdp(<2 x i64>, <2 x i64>)
define <16 x i8> @testVSLV(<16 x i8> %a, <16 x i8> %b) {
entry:
%0 = tail call <16 x i8> @llvm.ppc.altivec.vslv(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %0
; CHECK-LABEL: testVSLV
; CHECK: vslv 2, 2, 3
; CHECK: blr
}
; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vslv(<16 x i8>, <16 x i8>)
; Function Attrs: nounwind readnone
define <16 x i8> @testVSRV(<16 x i8> %a, <16 x i8> %b) {
entry:
%0 = tail call <16 x i8> @llvm.ppc.altivec.vsrv(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %0
; CHECK-LABEL: testVSRV
; CHECK: vsrv 2, 2, 3
; CHECK: blr
}
; Function Attrs: nounwind readnone
declare <16 x i8> @llvm.ppc.altivec.vsrv(<16 x i8>, <16 x i8>)
declare void @sink(...)