RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 20:51:52 +01:00
Code Issues Projects Releases Wiki Activity

Add support for the 'l' constraint.

Browse Source 
Patch by Jack Carter.

llvm-svn: 156294
This commit is contained in:
Eric Christopher 2012-05-07 06:25:15 +00:00
parent af8eabbbd8
commit 87e8163c57
2 changed files with 18 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -3001,6 +3001,7 @@ getConstraintType(const std::string &Constraint) const
// backwards compatibility. // backwards compatibility.
// 'c' : A register suitable for use in an indirect // 'c' : A register suitable for use in an indirect
// jump. This will always be $25 for -mabicalls. // jump. This will always be $25 for -mabicalls.
// 'l' : The lo register.
if (Constraint.size() == 1) { if (Constraint.size() == 1) {
switch (Constraint[0]) { switch (Constraint[0]) {
default : break; default : break;
@ -3008,6 +3009,7 @@ getConstraintType(const std::string &Constraint) const
case 'y': case 'y':
case 'f': case 'f':
case 'c': case 'c':
case 'l':
return C_RegisterClass; return C_RegisterClass;
} }
} }
@ -3042,6 +3044,7 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
weight = CW_Register; weight = CW_Register;
break; break;
case 'c': // $25 for indirect jumps case 'c': // $25 for indirect jumps
case 'l': // lo register
if (type->isIntegerTy()) if (type->isIntegerTy())
weight = CW_SpecificReg; weight = CW_SpecificReg;
break; break;
@ -3090,6 +3093,10 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass); return std::make_pair((unsigned)Mips::T9, &Mips::CPURegsRegClass);
assert(VT == MVT::i64 && "Unexpected type."); assert(VT == MVT::i64 && "Unexpected type.");
return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass); return std::make_pair((unsigned)Mips::T9_64, &Mips::CPU64RegsRegClass);
case 'l': // register suitable for indirect jump
if (VT == MVT::i32)
return std::make_pair((unsigned)Mips::LO, &Mips::HILORegClass);
return std::make_pair((unsigned)Mips::LO64, &Mips::HILO64RegClass);
} }
} }
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);

11
test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
View File

@ -29,5 +29,16 @@ entry:
; CHECK: #NO_APP ; CHECK: #NO_APP
tail call i32 asm sideeffect "addi $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind tail call i32 asm sideeffect "addi $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind
; Now l with 1024: make sure register lo is picked. We do this by checking the instruction
; after the inline expression for a mflo to pull the value out of lo.
; CHECK: #APP
; CHECK-NEXT: mtlo ${{[0-9]+}}
; CHECK-NEXT: madd ${{[0-9]+}},${{[0-9]+}}
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: mflo ${{[0-9]+}}
%bosco = alloca i32, align 4
call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1,$2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
store volatile i32 %4, i32* %bosco, align 4
ret i32 0 ret i32 0
} }