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[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).

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llvm-svn: 304954
This commit is contained in:
Eugene Zelenko 2017-06-07 23:53:32 +00:00
parent 285d868803
commit 88025fac90
20 changed files with 287 additions and 196 deletions
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37
include/llvm/CodeGen/DFAPacketizer.h
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@ -1,4 +1,4 @@
//=- llvm/CodeGen/DFAPacketizer.h - DFA Packetizer for VLIW ---*- C++ -*-=====//
//===- llvm/CodeGen/DFAPacketizer.h - DFA Packetizer for VLIW ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -29,17 +29,22 @@
#include "llvm/ADT/DenseMap.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/ScheduleDAGMutation.h"
#include <cstdint>
#include <map>
#include <memory>
#include <utility>
#include <vector>
namespace llvm {
class MCInstrDesc;
class DefaultVLIWScheduler;
class InstrItineraryData;
class MachineFunction;
class MachineInstr;
class MachineLoopInfo;
class MachineDominatorTree;
class InstrItineraryData;
class DefaultVLIWScheduler;
class MCInstrDesc;
class SUnit;
class TargetInstrInfo;
// --------------------------------------------------------------------
// Definitions shared between DFAPacketizer.cpp and DFAPacketizerEmitter.cpp
@ -64,17 +69,18 @@ class SUnit;
#define DFA_MAX_RESTERMS 4 // The max # of AND'ed resource terms.
#define DFA_MAX_RESOURCES 16 // The max # of resource bits in one term.
typedef uint64_t DFAInput;
typedef int64_t DFAStateInput;
using DFAInput = uint64_t;
using DFAStateInput = int64_t;
#define DFA_TBLTYPE "int64_t" // For generating DFAStateInputTable.
// --------------------------------------------------------------------
class DFAPacketizer {
private:
typedef std::pair<unsigned, DFAInput> UnsignPair;
using UnsignPair = std::pair<unsigned, DFAInput>;
const InstrItineraryData *InstrItins;
int CurrentState;
int CurrentState = 0;
const DFAStateInput (*DFAStateInputTable)[2];
const unsigned *DFAStateEntryTable;
@ -101,24 +107,23 @@ public:
// Check if the resources occupied by a MCInstrDesc are available in
// the current state.
bool canReserveResources(const llvm::MCInstrDesc *MID);
bool canReserveResources(const MCInstrDesc *MID);
// Reserve the resources occupied by a MCInstrDesc and change the current
// state to reflect that change.
void reserveResources(const llvm::MCInstrDesc *MID);
void reserveResources(const MCInstrDesc *MID);
// Check if the resources occupied by a machine instruction are available
// in the current state.
bool canReserveResources(llvm::MachineInstr &MI);
bool canReserveResources(MachineInstr &MI);
// Reserve the resources occupied by a machine instruction and change the
// current state to reflect that change.
void reserveResources(llvm::MachineInstr &MI);
void reserveResources(MachineInstr &MI);
const InstrItineraryData *getInstrItins() const { return InstrItins; }
};
// VLIWPacketizerList implements a simple VLIW packetizer using DFA. The
// packetizer works on machine basic blocks. For each instruction I in BB,
// the packetizer consults the DFA to see if machine resources are available
@ -205,6 +210,6 @@ public:
void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation);
};
} // namespace llvm
} // end namespace llvm
#endif
#endif // LLVM_CODEGEN_DFAPACKETIZER_H

42
include/llvm/CodeGen/ExecutionDepsFix.h
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@ -1,4 +1,4 @@
//===- llvm/CodeGen/ExecutionDepsFix.h - Execution Dependency Fix -*- C++ -*-=//
//==- llvm/CodeGen/ExecutionDepsFix.h - Execution Dependency Fix -*- C++ -*-==//
//
// The LLVM Compiler Infrastructure
//
@ -20,19 +20,30 @@
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_EXECUTIONDEPSFIX_H
#define LLVM_CODEGEN_EXECUTIONDEPSFIX_H
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/LivePhysRegs.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/Pass.h"
#include "llvm/Support/Allocator.h"
#include "llvm/Support/MathExtras.h"
#include <cassert>
#include <limits>
#include <utility>
#include <vector>
namespace llvm {
class MachineBasicBlock;
class MachineInstr;
class TargetInstrInfo;
/// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track
/// of execution domains.
///
@ -50,7 +61,7 @@ namespace llvm {
/// domains.
struct DomainValue {
// Basic reference counting.
unsigned Refs;
unsigned Refs = 0;
// Bitmask of available domains. For an open DomainValue, it is the still
// possible domains for collapsing. For a collapsed DomainValue it is the
@ -65,6 +76,8 @@ struct DomainValue {
// Twiddleable instructions using or defining these registers.
SmallVector<MachineInstr*, 8> Instrs;
DomainValue() { clear(); }
// A collapsed DomainValue has no instructions to twiddle - it simply keeps
// track of the domains where the registers are already available.
bool isCollapsed() const { return Instrs.empty(); }
@ -97,8 +110,6 @@ struct DomainValue {
return countTrailingZeros(AvailableDomains);
}
DomainValue() : Refs(0) { clear(); }
// Clear this DomainValue and point to next which has all its data.
void clear() {
AvailableDomains = 0;
@ -136,29 +147,27 @@ class ExecutionDepsFix : public MachineFunctionPass {
// Keeps clearance and domain information for all registers. Note that this
// is different from the usual definition notion of liveness. The CPU
// doesn't care whether or not we consider a register killed.
LiveReg *OutRegs;
LiveReg *OutRegs = nullptr;
// Whether we have gotten to this block in primary processing yet.
bool PrimaryCompleted;
bool PrimaryCompleted = false;
// The number of predecessors for which primary processing has completed
unsigned IncomingProcessed;
unsigned IncomingProcessed = 0;
// The value of `IncomingProcessed` at the start of primary processing
unsigned PrimaryIncoming;
unsigned PrimaryIncoming = 0;
// The number of predecessors for which all processing steps are done.
unsigned IncomingCompleted;
unsigned IncomingCompleted = 0;
MBBInfo()
: OutRegs(nullptr), PrimaryCompleted(false), IncomingProcessed(0),
PrimaryIncoming(0), IncomingCompleted(0) {}
MBBInfo() = default;
};
typedef DenseMap<MachineBasicBlock *, MBBInfo> MBBInfoMap;
using MBBInfoMap = DenseMap<MachineBasicBlock *, MBBInfo>;
MBBInfoMap MBBInfos;
/// List of undefined register reads in this block in forward order.
std::vector<std::pair<MachineInstr*, unsigned> > UndefReads;
std::vector<std::pair<MachineInstr *, unsigned>> UndefReads;
/// Storage for register unit liveness.
LivePhysRegs LiveRegSet;
@ -166,6 +175,7 @@ class ExecutionDepsFix : public MachineFunctionPass {
/// Current instruction number.
/// The first instruction in each basic block is 0.
int CurInstr;
public:
ExecutionDepsFix(char &PassID, const TargetRegisterClass &RC)
: MachineFunctionPass(PassID), RC(&RC), NumRegs(RC.getNumRegs()) {}
@ -217,4 +227,4 @@ private:
} // end namepsace llvm
#endif
#endif // LLVM_CODEGEN_EXECUTIONDEPSFIX_H

37
include/llvm/CodeGen/FastISel.h
View File

@ -17,6 +17,7 @@
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/IR/Attributes.h"
@ -30,19 +31,43 @@
#include <algorithm>
#include <cstdint>
#include <utility>
#include <vector>
namespace llvm {
class AllocaInst;
class BasicBlock;
class CallInst;
class Constant;
class ConstantFP;
class DataLayout;
class FunctionLoweringInfo;
class LoadInst;
class MachineConstantPool;
class MachineFrameInfo;
class MachineFunction;
class MachineInstr;
class MachineMemOperand;
class MachineOperand;
class MachineRegisterInfo;
class MCContext;
class MCInstrDesc;
class MCSymbol;
class TargetInstrInfo;
class TargetLibraryInfo;
class TargetMachine;
class TargetRegisterClass;
class TargetRegisterInfo;
class Type;
class User;
class Value;
/// \brief This is a fast-path instruction selection class that generates poor
/// code and doesn't support illegal types or non-trivial lowering, but runs
/// quickly.
class FastISel {
public:
typedef TargetLoweringBase::ArgListEntry ArgListEntry;
typedef TargetLoweringBase::ArgListTy ArgListTy;
using ArgListEntry = TargetLoweringBase::ArgListEntry;
using ArgListTy = TargetLoweringBase::ArgListTy;
struct CallLoweringInfo {
Type *RetTy = nullptr;
bool RetSExt : 1;
@ -202,6 +227,8 @@ protected:
MachineInstr *EmitStartPt;
public:
virtual ~FastISel();
/// \brief Return the position of the last instruction emitted for
/// materializing constants for use in the current block.
MachineInstr *getLastLocalValue() { return LastLocalValue; }
@ -293,8 +320,6 @@ public:
/// \brief Reset InsertPt to the given old insert position.
void leaveLocalValueArea(SavePoint Old);
virtual ~FastISel();
protected:
explicit FastISel(FunctionLoweringInfo &FuncInfo,
const TargetLibraryInfo *LibInfo,
@ -334,7 +359,7 @@ protected:
/// \brief This method is called by target-independent code to request that an
/// instruction with the given type, opcode, and register and immediate
// operands be emitted.
/// operands be emitted.
virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
bool Op0IsKill, uint64_t Imm);

33
include/llvm/CodeGen/FunctionLoweringInfo.h
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@ -1,4 +1,4 @@
//===-- FunctionLoweringInfo.h - Lower functions from LLVM IR to CodeGen --===//
//===- FunctionLoweringInfo.h - Lower functions from LLVM IR to CodeGen ---===//
//
// The LLVM Compiler Infrastructure
//
@ -23,29 +23,28 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Value.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include <cassert>
#include <utility>
#include <vector>
namespace llvm {
class AllocaInst;
class Argument;
class BasicBlock;
class BranchProbabilityInfo;
class Function;
class GlobalVariable;
class Instruction;
class MachineInstr;
class MachineBasicBlock;
class MachineFunction;
class MachineModuleInfo;
class MachineInstr;
class MachineRegisterInfo;
class SelectionDAG;
class MVT;
class SelectionDAG;
class TargetLowering;
class Value;
//===--------------------------------------------------------------------===//
/// FunctionLoweringInfo - This contains information that is global to a
@ -74,25 +73,24 @@ public:
/// A map from swifterror value in a basic block to the virtual register it is
/// currently represented by.
llvm::DenseMap<std::pair<const MachineBasicBlock *, const Value *>, unsigned>
DenseMap<std::pair<const MachineBasicBlock *, const Value *>, unsigned>
SwiftErrorVRegDefMap;
/// A list of upward exposed vreg uses that need to be satisfied by either a
/// copy def or a phi node at the beginning of the basic block representing
/// the predecessor(s) swifterror value.
llvm::DenseMap<std::pair<const MachineBasicBlock *, const Value *>, unsigned>
DenseMap<std::pair<const MachineBasicBlock *, const Value *>, unsigned>
SwiftErrorVRegUpwardsUse;
/// The swifterror argument of the current function.
const Value *SwiftErrorArg;
typedef SmallVector<const Value*, 1> SwiftErrorValues;
using SwiftErrorValues = SmallVector<const Value*, 1>;
/// A function can only have a single swifterror argument. And if it does
/// have a swifterror argument, it must be the first entry in
/// SwiftErrorVals.
SwiftErrorValues SwiftErrorVals;
/// Get or create the swifterror value virtual register in
/// SwiftErrorVRegDefMap for this basic block.
unsigned getOrCreateSwiftErrorVReg(const MachineBasicBlock *,
@ -118,7 +116,7 @@ public:
/// slot), and we track that here.
struct StatepointSpillMap {
typedef DenseMap<const Value *, Optional<int>> SlotMapTy;
using SlotMapTy = DenseMap<const Value *, Optional<int>>;
/// Maps uniqued llvm IR values to the slots they were spilled in. If a
/// value is mapped to None it means we visited the value but didn't spill
@ -172,8 +170,9 @@ public:
struct LiveOutInfo {
unsigned NumSignBits : 31;
unsigned IsValid : 1;
KnownBits Known;
LiveOutInfo() : NumSignBits(0), IsValid(true), Known(1) {}
KnownBits Known = 1;
LiveOutInfo() : NumSignBits(0), IsValid(true) {}
};
/// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND)
@ -298,4 +297,4 @@ private:
} // end namespace llvm
#endif
#endif // LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H

38
include/llvm/CodeGen/GCMetadata.h
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@ -1,4 +1,4 @@
//===-- GCMetadata.h - Garbage collector metadata ---------------*- C++ -*-===//
//===- GCMetadata.h - Garbage collector metadata ----------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -36,15 +36,20 @@
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/Pass.h"
#include <algorithm>
#include <cstddef>
#include <cstdint>
#include <memory>
#include <utility>
#include <vector>
namespace llvm {
class AsmPrinter;
class Constant;
class Function;
class MCSymbol;
/// GCPoint - Metadata for a collector-safe point in machine code.
@ -62,20 +67,20 @@ struct GCPoint {
/// collector.
struct GCRoot {
int Num; ///< Usually a frame index.
int StackOffset; ///< Offset from the stack pointer.
int StackOffset = -1; ///< Offset from the stack pointer.
const Constant *Metadata; ///< Metadata straight from the call
///< to llvm.gcroot.
GCRoot(int N, const Constant *MD) : Num(N), StackOffset(-1), Metadata(MD) {}
GCRoot(int N, const Constant *MD) : Num(N), Metadata(MD) {}
};
/// Garbage collection metadata for a single function. Currently, this
/// information only applies to GCStrategies which use GCRoot.
class GCFunctionInfo {
public:
typedef std::vector<GCPoint>::iterator iterator;
typedef std::vector<GCRoot>::iterator roots_iterator;
typedef std::vector<GCRoot>::const_iterator live_iterator;
using iterator = std::vector<GCPoint>::iterator;
using roots_iterator = std::vector<GCRoot>::iterator;
using live_iterator = std::vector<GCRoot>::const_iterator;
private:
const Function &F;
@ -99,11 +104,9 @@ public:
~GCFunctionInfo();
/// getFunction - Return the function to which this metadata applies.
///
const Function &getFunction() const { return F; }
/// getStrategy - Return the GC strategy for the function.
///
GCStrategy &getStrategy() { return S; }
/// addStackRoot - Registers a root that lives on the stack. Num is the
@ -126,24 +129,20 @@ public:
}
/// getFrameSize/setFrameSize - Records the function's frame size.
///
uint64_t getFrameSize() const { return FrameSize; }
void setFrameSize(uint64_t S) { FrameSize = S; }
/// begin/end - Iterators for safe points.
///
iterator begin() { return SafePoints.begin(); }
iterator end() { return SafePoints.end(); }
size_t size() const { return SafePoints.size(); }
/// roots_begin/roots_end - Iterators for all roots in the function.
///
roots_iterator roots_begin() { return Roots.begin(); }
roots_iterator roots_end() { return Roots.end(); }
size_t roots_size() const { return Roots.size(); }
/// live_begin/live_end - Iterators for live roots at a given safe point.
///
live_iterator live_begin(const iterator &p) { return roots_begin(); }
live_iterator live_end(const iterator &p) { return roots_end(); }
size_t live_size(const iterator &p) const { return roots_size(); }
@ -166,7 +165,7 @@ public:
/// List of per function info objects. In theory, Each of these
/// may be associated with a different GC.
typedef std::vector<std::unique_ptr<GCFunctionInfo>> FuncInfoVec;
using FuncInfoVec = std::vector<std::unique_ptr<GCFunctionInfo>>;
FuncInfoVec::iterator funcinfo_begin() { return Functions.begin(); }
FuncInfoVec::iterator funcinfo_end() { return Functions.end(); }
@ -177,11 +176,11 @@ private:
/// Non-owning map to bypass linear search when finding the GCFunctionInfo
/// associated with a particular Function.
typedef DenseMap<const Function *, GCFunctionInfo *> finfo_map_type;
using finfo_map_type = DenseMap<const Function *, GCFunctionInfo *>;
finfo_map_type FInfoMap;
public:
typedef SmallVector<std::unique_ptr<GCStrategy>,1>::const_iterator iterator;
using iterator = SmallVector<std::unique_ptr<GCStrategy>, 1>::const_iterator;
static char ID;
@ -202,6 +201,7 @@ public:
/// will soon change.
GCFunctionInfo &getFunctionInfo(const Function &F);
};
}
#endif
} // end namespace llvm
#endif // LLVM_CODEGEN_GCMETADATA_H

25
include/llvm/CodeGen/GCMetadataPrinter.h
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@ -1,4 +1,4 @@
//===-- llvm/CodeGen/GCMetadataPrinter.h - Prints asm GC tables -*- C++ -*-===//
//===- llvm/CodeGen/GCMetadataPrinter.h - Prints asm GC tables --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -20,45 +20,48 @@
#ifndef LLVM_CODEGEN_GCMETADATAPRINTER_H
#define LLVM_CODEGEN_GCMETADATAPRINTER_H
#include "llvm/CodeGen/GCMetadata.h"
#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/Support/Registry.h"
namespace llvm {
class AsmPrinter;
class GCMetadataPrinter;
class GCModuleInfo;
class GCStrategy;
class Module;
/// GCMetadataPrinterRegistry - The GC assembly printer registry uses all the
/// defaults from Registry.
typedef Registry<GCMetadataPrinter> GCMetadataPrinterRegistry;
using GCMetadataPrinterRegistry = Registry<GCMetadataPrinter>;
/// GCMetadataPrinter - Emits GC metadata as assembly code. Instances are
/// created, managed, and owned by the AsmPrinter.
class GCMetadataPrinter {
private:
GCStrategy *S;
friend class AsmPrinter;
GCStrategy *S;
protected:
// May only be subclassed.
GCMetadataPrinter();
private:
public:
GCMetadataPrinter(const GCMetadataPrinter &) = delete;
GCMetadataPrinter &operator=(const GCMetadataPrinter &) = delete;
virtual ~GCMetadataPrinter();
public:
GCStrategy &getStrategy() { return *S; }
/// Called before the assembly for the module is generated by
/// the AsmPrinter (but after target specific hooks.)
virtual void beginAssembly(Module &M, GCModuleInfo &Info, AsmPrinter &AP) {}
/// Called after the assembly for the module is generated by
/// the AsmPrinter (but before target specific hooks)
virtual void finishAssembly(Module &M, GCModuleInfo &Info, AsmPrinter &AP) {}
virtual ~GCMetadataPrinter();
};
}
#endif
} // end namespace llvm
#endif // LLVM_CODEGEN_GCMETADATAPRINTER_H

2
include/llvm/CodeGen/GCStrategy.h
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@ -174,7 +174,7 @@ public:
/// Note that to use a custom GCMetadataPrinter w/gc.roots, you must also
/// register your GCMetadataPrinter subclass with the
/// GCMetadataPrinterRegistery as well.
typedef Registry<GCStrategy> GCRegistry;
using GCRegistry = Registry<GCStrategy>;
} // end namespace llvm

3
include/llvm/CodeGen/LexicalScopes.h
View File

@ -31,12 +31,13 @@ namespace llvm {
class MachineBasicBlock;
class MachineFunction;
class MachineInstr;
class MDNode;
//===----------------------------------------------------------------------===//
/// InsnRange - This is used to track range of instructions with identical
/// lexical scope.
///
typedef std::pair<const MachineInstr *, const MachineInstr *> InsnRange;
using InsnRange = std::pair<const MachineInstr *, const MachineInstr *>;
//===----------------------------------------------------------------------===//
/// LexicalScope - This class is used to track scope information.

17
include/llvm/CodeGen/RegAllocRegistry.h
View File

@ -1,4 +1,4 @@
//===-- llvm/CodeGen/RegAllocRegistry.h -------------------------*- C++ -*-===//
//===- llvm/CodeGen/RegAllocRegistry.h --------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -19,16 +19,16 @@
namespace llvm {
class FunctionPass;
//===----------------------------------------------------------------------===//
///
/// RegisterRegAlloc class - Track the registration of register allocators.
///
//===----------------------------------------------------------------------===//
class RegisterRegAlloc : public MachinePassRegistryNode {
public:
typedef FunctionPass *(*FunctionPassCtor)();
using FunctionPassCtor = FunctionPass *(*)();
static MachinePassRegistry Registry;
@ -36,22 +36,26 @@ public:
: MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
Registry.Add(this);
}
~RegisterRegAlloc() { Registry.Remove(this); }
// Accessors.
//
RegisterRegAlloc *getNext() const {
return (RegisterRegAlloc *)MachinePassRegistryNode::getNext();
}
static RegisterRegAlloc *getList() {
return (RegisterRegAlloc *)Registry.getList();
}
static FunctionPassCtor getDefault() {
return (FunctionPassCtor)Registry.getDefault();
}
static void setDefault(FunctionPassCtor C) {
Registry.setDefault((MachinePassCtor)C);
}
static void setListener(MachinePassRegistryListener *L) {
Registry.setListener(L);
}
@ -59,5 +63,4 @@ public:
} // end namespace llvm
#endif
#endif // LLVM_CODEGEN_REGALLOCREGISTRY_H

11
include/llvm/CodeGen/StackProtector.h
View File

@ -19,17 +19,20 @@
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/Triple.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/ValueMap.h"
#include "llvm/Pass.h"
#include "llvm/Target/TargetLowering.h"
namespace llvm {
class BasicBlock;
class DominatorTree;
class Function;
class Instruction;
class Module;
class PHINode;
class TargetLoweringBase;
class TargetMachine;
class Type;
class StackProtector : public FunctionPass {
public:
@ -47,7 +50,7 @@ public:
};
/// A mapping of AllocaInsts to their required SSP layout.
typedef ValueMap<const AllocaInst *, SSPLayoutKind> SSPLayoutMap;
using SSPLayoutMap = ValueMap<const AllocaInst *, SSPLayoutKind>;
private:
const TargetMachine *TM = nullptr;

37
include/llvm/CodeGen/TailDuplicator.h
View File

@ -1,4 +1,4 @@
//===-- llvm/CodeGen/TailDuplicator.h ---------------------------*- C++ -*-===//
//===- llvm/CodeGen/TailDuplicator.h ----------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -15,19 +15,27 @@
#ifndef LLVM_CODEGEN_TAILDUPLICATOR_H
#define LLVM_CODEGEN_TAILDUPLICATOR_H
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineSSAUpdater.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <utility>
#include <vector>
namespace llvm {
extern cl::opt<unsigned> TailDupIndirectBranchSize;
class MachineBasicBlock;
class MachineBranchProbabilityInfo;
class MachineFunction;
class MachineInstr;
class MachineModuleInfo;
class MachineRegisterInfo;
class TargetRegisterInfo;
/// Utility class to perform tail duplication.
class TailDuplicator {
@ -46,7 +54,7 @@ class TailDuplicator {
// For each virtual register in SSAUpdateVals keep a list of source virtual
// registers.
typedef std::vector<std::pair<MachineBasicBlock *, unsigned>> AvailableValsTy;
using AvailableValsTy = std::vector<std::pair<MachineBasicBlock *, unsigned>>;
DenseMap<unsigned, AvailableValsTy> SSAUpdateVals;
@ -62,11 +70,14 @@ public:
void initMF(MachineFunction &MF,
const MachineBranchProbabilityInfo *MBPI,
bool LayoutMode, unsigned TailDupSize = 0);
bool tailDuplicateBlocks();
static bool isSimpleBB(MachineBasicBlock *TailBB);
bool shouldTailDuplicate(bool IsSimple, MachineBasicBlock &TailBB);
/// Returns true if TailBB can successfully be duplicated into PredBB
bool canTailDuplicate(MachineBasicBlock *TailBB, MachineBasicBlock *PredBB);
/// Tail duplicate a single basic block into its predecessors, and then clean
/// up.
/// If \p DuplicatePreds is not null, it will be updated to contain the list
@ -77,10 +88,10 @@ public:
bool IsSimple, MachineBasicBlock *MBB,
MachineBasicBlock *ForcedLayoutPred,
SmallVectorImpl<MachineBasicBlock*> *DuplicatedPreds = nullptr,
llvm::function_ref<void(MachineBasicBlock *)> *RemovalCallback = nullptr);
function_ref<void(MachineBasicBlock *)> *RemovalCallback = nullptr);
private:
typedef TargetInstrInfo::RegSubRegPair RegSubRegPair;
using RegSubRegPair = TargetInstrInfo::RegSubRegPair;
void addSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
MachineBasicBlock *BB);
@ -112,9 +123,9 @@ private:
void removeDeadBlock(
MachineBasicBlock *MBB,
llvm::function_ref<void(MachineBasicBlock *)> *RemovalCallback = nullptr);
function_ref<void(MachineBasicBlock *)> *RemovalCallback = nullptr);
};
} // End llvm namespace
} // end namespace llvm
#endif
#endif // LLVM_CODEGEN_TAILDUPLICATOR_H

3
include/llvm/CodeGen/TargetSchedule.h
View File

@ -16,6 +16,7 @@
#ifndef LLVM_CODEGEN_TARGETSCHEDULE_H
#define LLVM_CODEGEN_TARGETSCHEDULE_H
#include "llvm/ADT/Optional.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/MCSchedule.h"
@ -123,7 +124,7 @@ public:
}
#endif
typedef const MCWriteProcResEntry *ProcResIter;
using ProcResIter = const MCWriteProcResEntry *;
// \brief Get an iterator into the processor resources consumed by this
// scheduling class.

21
lib/CodeGen/AsmPrinter/OcamlGCPrinter.cpp
View File

@ -1,4 +1,4 @@
//===-- OcamlGCPrinter.cpp - Ocaml frametable emitter ---------------------===//
//===- OcamlGCPrinter.cpp - Ocaml frametable emitter ----------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -12,22 +12,26 @@
//===----------------------------------------------------------------------===//
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Twine.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/GCMetadata.h"
#include "llvm/CodeGen/GCMetadataPrinter.h"
#include "llvm/CodeGen/GCs.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/Mangler.h"
#include "llvm/IR/Module.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDirectives.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Target/TargetLoweringObjectFile.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cctype>
#include <cstddef>
#include <cstdint>
#include <string>
using namespace llvm;
namespace {
@ -37,7 +41,8 @@ public:
void beginAssembly(Module &M, GCModuleInfo &Info, AsmPrinter &AP) override;
void finishAssembly(Module &M, GCModuleInfo &Info, AsmPrinter &AP) override;
};
}
} // end anonymous namespace
static GCMetadataPrinterRegistry::Add<OcamlGCMetadataPrinter>
Y("ocaml", "ocaml 3.10-compatible collector");
@ -50,7 +55,7 @@ static void EmitCamlGlobal(const Module &M, AsmPrinter &AP, const char *Id) {
std::string SymName;
SymName += "caml";
size_t Letter = SymName.size();
SymName.append(MId.begin(), find(MId, '.'));
SymName.append(MId.begin(), llvm::find(MId, '.'));
SymName += "__";
SymName += Id;

67
lib/CodeGen/DFAPacketizer.cpp
View File

@ -23,49 +23,59 @@
//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "packets"
#include "llvm/CodeGen/DFAPacketizer.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBundle.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <iterator>
#include <memory>
#include <vector>
using namespace llvm;
#define DEBUG_TYPE "packets"
static cl::opt<unsigned> InstrLimit("dfa-instr-limit", cl::Hidden,
cl::init(0), cl::desc("If present, stops packetizing after N instructions"));
static unsigned InstrCount = 0;
// --------------------------------------------------------------------
// Definitions shared between DFAPacketizer.cpp and DFAPacketizerEmitter.cpp
namespace {
DFAInput addDFAFuncUnits(DFAInput Inp, unsigned FuncUnits) {
static DFAInput addDFAFuncUnits(DFAInput Inp, unsigned FuncUnits) {
return (Inp << DFA_MAX_RESOURCES) | FuncUnits;
}
}
/// Return the DFAInput for an instruction class input vector.
/// This function is used in both DFAPacketizer.cpp and in
/// DFAPacketizerEmitter.cpp.
DFAInput getDFAInsnInput(const std::vector<unsigned> &InsnClass) {
/// Return the DFAInput for an instruction class input vector.
/// This function is used in both DFAPacketizer.cpp and in
/// DFAPacketizerEmitter.cpp.
static DFAInput getDFAInsnInput(const std::vector<unsigned> &InsnClass) {
DFAInput InsnInput = 0;
assert((InsnClass.size() <= DFA_MAX_RESTERMS) &&
"Exceeded maximum number of DFA terms");
for (auto U : InsnClass)
InsnInput = addDFAFuncUnits(InsnInput, U);
return InsnInput;
}
}
// --------------------------------------------------------------------
DFAPacketizer::DFAPacketizer(const InstrItineraryData *I,
const DFAStateInput (*SIT)[2],
const unsigned *SET):
InstrItins(I), CurrentState(0), DFAStateInputTable(SIT),
DFAStateEntryTable(SET) {
InstrItins(I), DFAStateInputTable(SIT), DFAStateEntryTable(SET) {
// Make sure DFA types are large enough for the number of terms & resources.
static_assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <=
(8 * sizeof(DFAInput)),
@ -75,7 +85,6 @@ DFAPacketizer::DFAPacketizer(const InstrItineraryData *I,
"(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAStateInput");
}
// Read the DFA transition table and update CachedTable.
//
// Format of the transition tables:
@ -97,7 +106,6 @@ void DFAPacketizer::ReadTable(unsigned int state) {
DFAStateInputTable[i][1];
}
// Return the DFAInput for an instruction class.
DFAInput DFAPacketizer::getInsnInput(unsigned InsnClass) {
// Note: this logic must match that in DFAPacketizerDefs.h for input vectors.
@ -112,16 +120,14 @@ DFAInput DFAPacketizer::getInsnInput(unsigned InsnClass) {
return InsnInput;
}
// Return the DFAInput for an instruction class input vector.
DFAInput DFAPacketizer::getInsnInput(const std::vector<unsigned> &InsnClass) {
return getDFAInsnInput(InsnClass);
}
// Check if the resources occupied by a MCInstrDesc are available in the
// current state.
bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) {
bool DFAPacketizer::canReserveResources(const MCInstrDesc *MID) {
unsigned InsnClass = MID->getSchedClass();
DFAInput InsnInput = getInsnInput(InsnClass);
UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput);
@ -129,10 +135,9 @@ bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) {
return CachedTable.count(StateTrans) != 0;
}
// Reserve the resources occupied by a MCInstrDesc and change the current
// state to reflect that change.
void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) {
void DFAPacketizer::reserveResources(const MCInstrDesc *MID) {
unsigned InsnClass = MID->getSchedClass();
DFAInput InsnInput = getInsnInput(InsnClass);
UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput);
@ -141,24 +146,22 @@ void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) {
CurrentState = CachedTable[StateTrans];
}
// Check if the resources occupied by a machine instruction are available
// in the current state.
bool DFAPacketizer::canReserveResources(llvm::MachineInstr &MI) {
const llvm::MCInstrDesc &MID = MI.getDesc();
bool DFAPacketizer::canReserveResources(MachineInstr &MI) {
const MCInstrDesc &MID = MI.getDesc();
return canReserveResources(&MID);
}
// Reserve the resources occupied by a machine instruction and change the
// current state to reflect that change.
void DFAPacketizer::reserveResources(llvm::MachineInstr &MI) {
const llvm::MCInstrDesc &MID = MI.getDesc();
void DFAPacketizer::reserveResources(MachineInstr &MI) {
const MCInstrDesc &MID = MI.getDesc();
reserveResources(&MID);
}
namespace llvm {
// This class extends ScheduleDAGInstrs and overrides the schedule method
// to build the dependence graph.
class DefaultVLIWScheduler : public ScheduleDAGInstrs {
@ -166,9 +169,11 @@ private:
AliasAnalysis *AA;
/// Ordered list of DAG postprocessing steps.
std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
public:
DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,
AliasAnalysis *AA);
// Actual scheduling work.
void schedule() override;
@ -176,11 +181,12 @@ public:
void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation) {
Mutations.push_back(std::move(Mutation));
}
protected:
void postprocessDAG();
};
}
} // end namespace llvm
DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF,
MachineLoopInfo &MLI,
@ -189,21 +195,18 @@ DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF,
CanHandleTerminators = true;
}
/// Apply each ScheduleDAGMutation step in order.
void DefaultVLIWScheduler::postprocessDAG() {
for (auto &M : Mutations)
M->apply(this);
}
void DefaultVLIWScheduler::schedule() {
// Build the scheduling graph.
buildSchedGraph(AA);
postprocessDAG();
}
VLIWPacketizerList::VLIWPacketizerList(MachineFunction &mf,
MachineLoopInfo &mli, AliasAnalysis *aa)
: MF(mf), TII(mf.getSubtarget().getInstrInfo()), AA(aa) {
@ -211,13 +214,11 @@ VLIWPacketizerList::VLIWPacketizerList(MachineFunction &mf,
VLIWScheduler = new DefaultVLIWScheduler(MF, mli, AA);
}
VLIWPacketizerList::~VLIWPacketizerList() {
delete VLIWScheduler;
delete ResourceTracker;
}
// End the current packet, bundle packet instructions and reset DFA state.
void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MI) {
@ -237,7 +238,6 @@ void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
DEBUG(dbgs() << "End packet\n");
}
// Bundle machine instructions into packets.
void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
MachineBasicBlock::iterator BeginItr,
@ -336,7 +336,6 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
VLIWScheduler->finishBlock();
}
// Add a DAG mutation object to the ordered list.
void VLIWPacketizerList::addMutation(
std::unique_ptr<ScheduleDAGMutation> Mutation) {

16
lib/CodeGen/GCMetadata.cpp
View File

@ -11,22 +11,27 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/GCMetadata.h"
#include "llvm/CodeGen/GCStrategy.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/IR/Function.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include <algorithm>
#include <cassert>
#include <memory>
#include <string>
using namespace llvm;
namespace {
class Printer : public FunctionPass {
static char ID;
raw_ostream &OS;
public:
@ -38,7 +43,8 @@ public:
bool runOnFunction(Function &F) override;
bool doFinalization(Module &M) override;
};
}
} // end anonymous namespace
INITIALIZE_PASS(GCModuleInfo, "collector-metadata",
"Create Garbage Collector Module Metadata", false, false)
@ -48,7 +54,7 @@ INITIALIZE_PASS(GCModuleInfo, "collector-metadata",
GCFunctionInfo::GCFunctionInfo(const Function &F, GCStrategy &S)
: F(F), S(S), FrameSize(~0LL) {}
GCFunctionInfo::~GCFunctionInfo() {}
GCFunctionInfo::~GCFunctionInfo() = default;
// -----------------------------------------------------------------------------
@ -67,7 +73,7 @@ GCFunctionInfo &GCModuleInfo::getFunctionInfo(const Function &F) {
return *I->second;
GCStrategy *S = getGCStrategy(F.getGC());
Functions.push_back(make_unique<GCFunctionInfo>(F, *S));
Functions.push_back(llvm::make_unique<GCFunctionInfo>(F, *S));
GCFunctionInfo *GFI = Functions.back().get();
FInfoMap[&F] = GFI;
return *GFI;

7
lib/CodeGen/GCMetadataPrinter.cpp
View File

@ -1,4 +1,4 @@
//===-- GCMetadataPrinter.cpp - Garbage collection infrastructure ---------===//
//===- GCMetadataPrinter.cpp - Garbage collection infrastructure ----------===//
//
// The LLVM Compiler Infrastructure
//
@ -12,10 +12,11 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/GCMetadataPrinter.h"
using namespace llvm;
LLVM_INSTANTIATE_REGISTRY(GCMetadataPrinterRegistry)
GCMetadataPrinter::GCMetadataPrinter() {}
GCMetadataPrinter::GCMetadataPrinter() = default;
GCMetadataPrinter::~GCMetadataPrinter() {}
GCMetadataPrinter::~GCMetadataPrinter() = default;

15
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -1,4 +1,4 @@
//===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
//===- SelectionDAGISel.cpp - Implement the SelectionDAGISel class --------===//
//
// The LLVM Compiler Infrastructure
//
@ -11,7 +11,6 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "ScheduleDAGSDNodes.h"
#include "SelectionDAGBuilder.h"
#include "llvm/ADT/APInt.h"
@ -32,6 +31,7 @@
#include "llvm/CodeGen/FastISel.h"
#include "llvm/CodeGen/FunctionLoweringInfo.h"
#include "llvm/CodeGen/GCMetadata.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
@ -39,21 +39,23 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/SchedulerRegistry.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/StackProtector.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/InstrTypes.h"
@ -64,6 +66,7 @@
#include "llvm/IR/Metadata.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/User.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Pass.h"
@ -89,6 +92,7 @@
#include <cassert>
#include <cstdint>
#include <iterator>
#include <limits>
#include <memory>
#include <string>
#include <utility>
@ -766,7 +770,6 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
<< " '" << BlockName << "'\n"; CurDAG->dump());
}
{
@ -1137,7 +1140,7 @@ static void processDbgDeclares(FunctionLoweringInfo *FuncInfo) {
// Check if the variable is a static alloca or a byval or inalloca
// argument passed in memory. If it is not, then we will ignore this
// intrinsic and handle this during isel like dbg.value.
int FI = INT_MAX;
int FI = std::numeric_limits<int>::max();
if (const auto *AI = dyn_cast<AllocaInst>(Address)) {
auto SI = FuncInfo->StaticAllocaMap.find(AI);
if (SI != FuncInfo->StaticAllocaMap.end())
@ -1145,7 +1148,7 @@ static void processDbgDeclares(FunctionLoweringInfo *FuncInfo) {
} else if (const auto *Arg = dyn_cast<Argument>(Address))
FI = FuncInfo->getArgumentFrameIndex(Arg);
if (FI == INT_MAX)
if (FI == std::numeric_limits<int>::max())
continue;
DIExpression *Expr = DI->getExpression();

4
lib/CodeGen/StackProtector.cpp
View File

@ -14,13 +14,13 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/StackProtector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/BranchProbabilityInfo.h"
#include "llvm/Analysis/EHPersonalities.h"
#include "llvm/Analysis/OptimizationDiagnosticInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/StackProtector.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/BasicBlock.h"
@ -29,6 +29,7 @@
#include "llvm/IR/DebugInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instruction.h"
@ -59,6 +60,7 @@ static cl::opt<bool> EnableSelectionDAGSP("enable-selectiondag-sp",
cl::init(true), cl::Hidden);
char StackProtector::ID = 0;
INITIALIZE_PASS_BEGIN(StackProtector, DEBUG_TYPE,
"Insert stack protectors", false, true)
INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)

14
lib/CodeGen/TailDuplication.cpp
View File

@ -1,4 +1,4 @@
//===-- TailDuplication.cpp - Duplicate blocks into predecessors' tails ---===//
//===- TailDuplication.cpp - Duplicate blocks into predecessors' tails ----===//
//
// The LLVM Compiler Infrastructure
//
@ -12,22 +12,25 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/TailDuplicator.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/Debug.h"
#include "llvm/Pass.h"
using namespace llvm;
#define DEBUG_TYPE "tailduplication"
namespace {
/// Perform tail duplication. Delegates to TailDuplicator
class TailDuplicatePass : public MachineFunctionPass {
TailDuplicator Duplicator;
public:
static char ID;
explicit TailDuplicatePass() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override;
@ -35,8 +38,9 @@ public:
void getAnalysisUsage(AnalysisUsage &AU) const override;
};
} // end anonymous namespace
char TailDuplicatePass::ID = 0;
}
char &llvm::TailDuplicateID = TailDuplicatePass::ID;

38
lib/CodeGen/TailDuplicator.cpp
View File

@ -1,4 +1,4 @@
//===-- TailDuplicator.cpp - Duplicate blocks into predecessors' tails ---===//
//===- TailDuplicator.cpp - Duplicate blocks into predecessors' tails -----===//
//
// The LLVM Compiler Infrastructure
//
@ -12,22 +12,36 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/TailDuplicator.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineSSAUpdater.h"
#include "llvm/CodeGen/TailDuplicator.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/Function.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <iterator>
#include <utility>
using namespace llvm;
#define DEBUG_TYPE "tailduplication"
@ -41,15 +55,13 @@ STATISTIC(NumTailDupRemoved,
STATISTIC(NumDeadBlocks, "Number of dead blocks removed");
STATISTIC(NumAddedPHIs, "Number of phis added");
namespace llvm {
// Heuristic for tail duplication.
static cl::opt<unsigned> TailDuplicateSize(
"tail-dup-size",
cl::desc("Maximum instructions to consider tail duplicating"), cl::init(2),
cl::Hidden);
cl::opt<unsigned> TailDupIndirectBranchSize(
static cl::opt<unsigned> TailDupIndirectBranchSize(
"tail-dup-indirect-size",
cl::desc("Maximum instructions to consider tail duplicating blocks that "
"end with indirect branches."), cl::init(20),
@ -138,7 +150,7 @@ bool TailDuplicator::tailDuplicateAndUpdate(
bool IsSimple, MachineBasicBlock *MBB,
MachineBasicBlock *ForcedLayoutPred,
SmallVectorImpl<MachineBasicBlock*> *DuplicatedPreds,
llvm::function_ref<void(MachineBasicBlock *)> *RemovalCallback) {
function_ref<void(MachineBasicBlock *)> *RemovalCallback) {
// Save the successors list.
SmallSetVector<MachineBasicBlock *, 8> Succs(MBB->succ_begin(),
MBB->succ_end());
@ -971,7 +983,7 @@ void TailDuplicator::appendCopies(MachineBasicBlock *MBB,
/// the CFG.
void TailDuplicator::removeDeadBlock(
MachineBasicBlock *MBB,
llvm::function_ref<void(MachineBasicBlock *)> *RemovalCallback) {
function_ref<void(MachineBasicBlock *)> *RemovalCallback) {
assert(MBB->pred_empty() && "MBB must be dead!");
DEBUG(dbgs() << "\nRemoving MBB: " << *MBB);
@ -985,5 +997,3 @@ void TailDuplicator::removeDeadBlock(
// Remove the block.
MBB->eraseFromParent();
}
} // End llvm namespace