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[InstCombine] add tests for missing vector icmp folds

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llvm-svn: 278768
This commit is contained in:
Sanjay Patel 2016-08-16 00:48:38 +00:00
parent e4d1ed48d7
commit 8812bdbcf4
2 changed files with 36 additions and 0 deletions
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24
test/Transforms/InstCombine/icmp.ll
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@ -1105,6 +1105,18 @@ define i1 @icmp_shl16(i32 %x) {
ret i1 %cmp
}
; FIXME: Vectors should fold the same way.
define <2 x i1> @icmp_shl16_vec(<2 x i32> %x) {
; CHECK-LABEL: @icmp_shl16_vec(
; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> %x, <i32 16, i32 16>
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> [[SHL]], <i32 2359296, i32 2359296>
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%shl = shl <2 x i32> %x, <i32 16, i32 16>
%cmp = icmp slt <2 x i32> %shl, <i32 2359296, i32 2359296>
ret <2 x i1> %cmp
}
define i1 @icmp_shl24(i32 %x) {
; CHECK-LABEL: @icmp_shl24(
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 %x to i8
@ -1148,6 +1160,18 @@ define i1 @icmp_shl_nsw_sge1(i32 %x) {
ret i1 %cmp
}
; FIXME: Vectors should fold the same way.
define <2 x i1> @icmp_shl_nsw_sge1_vec(<2 x i32> %x) {
; CHECK-LABEL: @icmp_shl_nsw_sge1_vec(
; CHECK-NEXT: [[SHL:%.*]] = shl nsw <2 x i32> %x, <i32 21, i32 21>
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> [[SHL]], zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;
%shl = shl nsw <2 x i32> %x, <i32 21, i32 21>
%cmp = icmp sge <2 x i32> %shl, <i32 1, i32 1>
ret <2 x i1> %cmp
}
; Checks for icmp (eq|ne) (shl x, C), 0
define i1 @icmp_shl_nsw_eq(i32 %x) {
; CHECK-LABEL: @icmp_shl_nsw_eq(

12
test/Transforms/InstCombine/shift.ll
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@ -605,6 +605,18 @@ define i1 @test33(i32 %X) {
ret i1 %tmp2
}
; FIXME: Vectors should fold the same way.
define <2 x i1> @test33vec(<2 x i32> %X) {
; CHECK-LABEL: @test33vec(
; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> %X, <i32 7, i32 7>
; CHECK-NEXT: [[TMP2:%.*]] = icmp slt <2 x i32> [[TMP1]], zeroinitializer
; CHECK-NEXT: ret <2 x i1> [[TMP2]]
;
%tmp1 = shl <2 x i32> %X, <i32 7, i32 7>
%tmp2 = icmp slt <2 x i32> %tmp1, zeroinitializer
ret <2 x i1> %tmp2
}
define i1 @test34(i32 %X) {
; CHECK-LABEL: @test34(
; CHECK-NEXT: ret i1 false