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Comment from code review
llvm-svn: 151178
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@ -362,6 +362,7 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
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unsigned Reg = MI->getOperand(OperIdx).getReg();
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// SSA defs do not have output/anti dependencies.
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// The current operand is a def, so we have at least one.
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if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
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return;
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