From 8830999b87cffbe527b9df17482d465eaba0afd4 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Mon, 6 Sep 2021 14:47:02 -0400 Subject: [PATCH] [DAGCombine] Prevent the transform of combine for multi-use operand The test is based on a miscompile example in: https://llvm.org/PR51321 Differential Revision: https://reviews.llvm.org/D107692 (cherry picked from commit e1e4bf174b09bcd4b25cd624f177537890bff785) --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 ++- test/CodeGen/AArch64/arm64-srl-and.ll | 6 ++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 4f730b2cf37..dc245f0d7b1 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -5133,8 +5133,9 @@ SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) { if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL)) return V; + // TODO: Rewrite this to return a new 'AND' instead of using CombineTo. if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && - VT.getSizeInBits() <= 64) { + VT.getSizeInBits() <= 64 && N0->hasOneUse()) { if (ConstantSDNode *ADDI = dyn_cast(N0.getOperand(1))) { if (ConstantSDNode *SRLI = dyn_cast(N1.getOperand(1))) { // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal diff --git a/test/CodeGen/AArch64/arm64-srl-and.ll b/test/CodeGen/AArch64/arm64-srl-and.ll index 2f024e444d2..c6b301b8e80 100644 --- a/test/CodeGen/AArch64/arm64-srl-and.ll +++ b/test/CodeGen/AArch64/arm64-srl-and.ll @@ -1,7 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=aarch64-linux-gnu -O3 < %s | FileCheck %s -; Disable the dagcombine if operand has multi use +; This used to miscompile: +; The 16-bit -1 should not become 32-bit -1 (sub w8, w8, #1). @g = global i16 0, align 4 define i32 @srl_and() { @@ -12,7 +13,8 @@ define i32 @srl_and() { ; CHECK-NEXT: mov w9, #50 ; CHECK-NEXT: ldrh w8, [x8] ; CHECK-NEXT: eor w8, w8, w9 -; CHECK-NEXT: sub w8, w8, #1 +; CHECK-NEXT: mov w9, #65535 +; CHECK-NEXT: add w8, w8, w9 ; CHECK-NEXT: and w0, w8, w8, lsr #16 ; CHECK-NEXT: ret entry: