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[AMDGPU] Set more flags on Real instructions

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This does not affect codegen, which only tests these flags on Pseudo
instructions, but might help llvm-mca which has to work with Real
instructions. In particular setting LGKM_CNT on DS instructions helps
with the problem identified in D104149.

Differential Revision: https://reviews.llvm.org/D104293
This commit is contained in:
Jay Foad 2021-06-15 13:15:42 +01:00
parent 965d5fb99e
commit 88474bed70
4 changed files with 20 additions and 9 deletions
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8
lib/Target/AMDGPU/BUFInstructions.td
View File

@ -110,6 +110,10 @@ class MTBUF_Real <MTBUF_Pseudo ps> :
let isPseudo = 0;
let isCodeGenOnly = 0;
let VM_CNT = 1;
let EXP_CNT = 1;
let MTBUF = 1;
// copy relevant pseudo op flags
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SubtargetPredicate = ps.SubtargetPredicate;
@ -341,6 +345,10 @@ class MUBUF_Real <MUBUF_Pseudo ps> :
let isPseudo = 0;
let isCodeGenOnly = 0;
let VM_CNT = 1;
let EXP_CNT = 1;
let MUBUF = 1;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;

1
lib/Target/AMDGPU/DSInstructions.td
View File

@ -58,6 +58,7 @@ class DS_Real <DS_Pseudo ds> :
let isPseudo = 0;
let isCodeGenOnly = 0;
let LGKM_CNT = 1;
let DS = 1;
let UseNamedOperandTable = 1;

4
lib/Target/AMDGPU/FLATInstructions.td
View File

@ -81,6 +81,8 @@ class FLAT_Real <bits<7> op, FLAT_Pseudo ps> :
let isPseudo = 0;
let isCodeGenOnly = 0;
let FLAT = 1;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
@ -88,6 +90,8 @@ class FLAT_Real <bits<7> op, FLAT_Pseudo ps> :
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SchedRW = ps.SchedRW;
let VM_CNT = ps.VM_CNT;
let LGKM_CNT = ps.LGKM_CNT;
// encoding fields
bits<8> vaddr;

16
lib/Target/AMDGPU/SMInstructions.td
View File

@ -57,11 +57,15 @@ class SM_Real <SM_Pseudo ps>
Instruction Opcode = !cast<Instruction>(NAME);
// copy relevant pseudo op flags
let LGKM_CNT = ps.LGKM_CNT;
let SMRD = ps.SMRD;
let mayStore = ps.mayStore;
let mayLoad = ps.mayLoad;
let hasSideEffects = ps.hasSideEffects;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SchedRW = ps.SchedRW;
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SMRD = ps.SMRD;
let SchedRW = ps.SchedRW;
let TSFlags = ps.TSFlags;
@ -700,12 +704,6 @@ class SMRD_Real_Load_IMM_ci <bits<5> op, SM_Load_Pseudo ps> :
let DecoderNamespace = "GFX7";
let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, CPol:$cpol);
let LGKM_CNT = ps.LGKM_CNT;
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
let hasSideEffects = ps.hasSideEffects;
let SchedRW = ps.SchedRW;
let Inst{7-0} = 0xff;
let Inst{8} = 0;
let Inst{14-9} = sbase{6-1};