From 88597bc560f47392f41f366fe96428b1ccbcffcd Mon Sep 17 00:00:00 2001 From: Shengchen Kan Date: Fri, 17 Apr 2020 20:26:26 +0800 Subject: [PATCH] [MC][Bugfix] Remove redundant parameter for relaxInstruction Summary: Before this patch, `relaxInstruction` takes three arguments, the first argument refers to the instruction before relaxation and the third argument is the output instruction after relaxation. There are two quite strange things: 1) The first argument's type is `const MCInst &`, the third argument's type is `MCInst &`, but they may be aliased to the same variable 2) The backends of ARM, AMDGPU, RISC-V, Hexagon assume that the third argument is a fresh uninitialized `MCInst` even if `relaxInstruction` may be called like `relaxInstruction(Relaxed, STI, Relaxed)` in a loop. In this patch, we drop the thrid argument, and let `relaxInstruction` directly modify the given instruction. Also, this patch fixes the bug https://bugs.llvm.org/show_bug.cgi?id=45580, which is introduced by D77851, and breaks the assumption of ARM, AMDGPU, RISC-V, Hexagon. Reviewers: Razer6, MaskRay, jyknight, asb, luismarques, enderby, rtaylor, colinl, bcain Reviewed By: Razer6, MaskRay, bcain Subscribers: bcain, nickdesaulniers, nathanchance, wuzish, annita.zhang, arsenm, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, tpr, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, Jim, lenary, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78364 --- include/llvm/MC/MCAsmBackend.h | 9 ++++----- lib/MC/MCAssembler.cpp | 4 ++-- lib/MC/MCObjectStreamer.cpp | 2 +- lib/MCA/CodeEmitter.cpp | 2 +- .../AArch64/MCTargetDesc/AArch64AsmBackend.cpp | 9 ++++----- .../AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp | 11 ++++++----- lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp | 10 +++++----- lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h | 4 ++-- lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h | 3 --- lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp | 3 --- .../Hexagon/MCTargetDesc/HexagonAsmBackend.cpp | 7 +++++-- .../Lanai/MCTargetDesc/LanaiAsmBackend.cpp | 4 ---- .../MSP430/MCTargetDesc/MSP430AsmBackend.cpp | 3 --- lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h | 11 ----------- .../PowerPC/MCTargetDesc/PPCAsmBackend.cpp | 4 ++-- .../RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 7 ++++--- lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h | 5 ++--- .../Sparc/MCTargetDesc/SparcAsmBackend.cpp | 4 ++-- .../SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp | 4 ---- .../MCTargetDesc/WebAssemblyAsmBackend.cpp | 3 --- lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp | 16 +++++++--------- test/MC/RISCV/rv64-relax-all.s | 15 +++++++++++++++ 22 files changed, 62 insertions(+), 78 deletions(-) create mode 100644 test/MC/RISCV/rv64-relax-all.s diff --git a/include/llvm/MC/MCAsmBackend.h b/include/llvm/MC/MCAsmBackend.h index c24e7c948b8..cc9f42023bc 100644 --- a/include/llvm/MC/MCAsmBackend.h +++ b/include/llvm/MC/MCAsmBackend.h @@ -161,12 +161,11 @@ public: /// Relax the instruction in the given fragment to the next wider instruction. /// - /// \param Inst The instruction to relax, which may be the same as the - /// output. + /// \param [out] Inst The instruction to relax, which is also the relaxed + /// instruction. /// \param STI the subtarget information for the associated instruction. - /// \param [out] Res On return, the relaxed instruction. - virtual void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const = 0; + virtual void relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const {}; /// @} diff --git a/lib/MC/MCAssembler.cpp b/lib/MC/MCAssembler.cpp index b36f45c3728..47b25c5a299 100644 --- a/lib/MC/MCAssembler.cpp +++ b/lib/MC/MCAssembler.cpp @@ -926,8 +926,8 @@ bool MCAssembler::relaxInstruction(MCAsmLayout &Layout, // Relax the fragment. - MCInst Relaxed; - getBackend().relaxInstruction(F.getInst(), *F.getSubtargetInfo(), Relaxed); + MCInst Relaxed = F.getInst(); + getBackend().relaxInstruction(Relaxed, *F.getSubtargetInfo()); // Encode the new instruction. // diff --git a/lib/MC/MCObjectStreamer.cpp b/lib/MC/MCObjectStreamer.cpp index c7b30d179cb..98b4f9b1fd9 100644 --- a/lib/MC/MCObjectStreamer.cpp +++ b/lib/MC/MCObjectStreamer.cpp @@ -408,7 +408,7 @@ void MCObjectStreamer::emitInstructionImpl(const MCInst &Inst, (Assembler.isBundlingEnabled() && Sec->isBundleLocked())) { MCInst Relaxed = Inst; while (getAssembler().getBackend().mayNeedRelaxation(Relaxed, STI)) - getAssembler().getBackend().relaxInstruction(Relaxed, STI, Relaxed); + getAssembler().getBackend().relaxInstruction(Relaxed, STI); emitInstToData(Relaxed, STI); return; } diff --git a/lib/MCA/CodeEmitter.cpp b/lib/MCA/CodeEmitter.cpp index 294107219cb..dcb92d253ba 100644 --- a/lib/MCA/CodeEmitter.cpp +++ b/lib/MCA/CodeEmitter.cpp @@ -25,7 +25,7 @@ CodeEmitter::getOrCreateEncodingInfo(unsigned MCID) { const MCInst &Inst = Sequence[MCID]; MCInst Relaxed(Sequence[MCID]); if (MAB.mayNeedRelaxation(Inst, STI)) - MAB.relaxInstruction(Inst, STI, Relaxed); + MAB.relaxInstruction(Relaxed, STI); EI.first = Code.size(); MCE.encodeInstruction(Relaxed, VecOS, Fixups, STI); diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp index 4e9bcb503bb..a5e78f19aeb 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp +++ b/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp @@ -93,8 +93,8 @@ public: bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override; - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override; + void relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const override; bool writeNopData(raw_ostream &OS, uint64_t Count) const override; void HandleAssemblerFlag(MCAssemblerFlag Flag) {} @@ -467,9 +467,8 @@ bool AArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, return int64_t(Value) != int64_t(int8_t(Value)); } -void AArch64AsmBackend::relaxInstruction(const MCInst &Inst, - const MCSubtargetInfo &STI, - MCInst &Res) const { +void AArch64AsmBackend::relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const { llvm_unreachable("AArch64AsmBackend::relaxInstruction() unimplemented"); } diff --git a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp index 07ab99ef94e..ea6e9038fd1 100644 --- a/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp +++ b/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp @@ -40,8 +40,8 @@ public: const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override; - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override; + void relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const override; bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const override; @@ -54,12 +54,13 @@ public: } //End anonymous namespace -void AMDGPUAsmBackend::relaxInstruction(const MCInst &Inst, - const MCSubtargetInfo &STI, - MCInst &Res) const { +void AMDGPUAsmBackend::relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const { + MCInst Res; unsigned RelaxedOpcode = AMDGPU::getSOPPWithRelaxation(Inst.getOpcode()); Res.setOpcode(RelaxedOpcode); Res.addOperand(Inst.getOperand(0)); + Inst = std::move(Res); return; } diff --git a/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp index 813406c0ecb..5407bc6f5ff 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -328,9 +328,8 @@ bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, return reasonForFixupRelaxation(Fixup, Value); } -void ARMAsmBackend::relaxInstruction(const MCInst &Inst, - const MCSubtargetInfo &STI, - MCInst &Res) const { +void ARMAsmBackend::relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const { unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode(), STI); // Sanity check w/ diagnostic if we get here w/ a bogus instruction. @@ -346,17 +345,18 @@ void ARMAsmBackend::relaxInstruction(const MCInst &Inst, // have to change the operands too. if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) && RelaxedOp == ARM::tHINT) { + MCInst Res; Res.setOpcode(RelaxedOp); Res.addOperand(MCOperand::createImm(0)); Res.addOperand(MCOperand::createImm(14)); Res.addOperand(MCOperand::createReg(0)); + Inst = std::move(Res); return; } // The rest of instructions we're relaxing have the same operands. // We just need to update to the proper opcode. - Res = Inst; - Res.setOpcode(RelaxedOp); + Inst.setOpcode(RelaxedOp); } bool ARMAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const { diff --git a/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h b/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h index 67722a5e5b6..38c7b30769b 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h +++ b/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h @@ -66,8 +66,8 @@ public: const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override; - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override; + void relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const override; bool writeNopData(raw_ostream &OS, uint64_t Count) const override; diff --git a/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h b/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h index 1e713db3814..62054c04d7d 100644 --- a/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h +++ b/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h @@ -62,9 +62,6 @@ public: return false; } - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override {} - bool writeNopData(raw_ostream &OS, uint64_t Count) const override; bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, diff --git a/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp b/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp index ba35a175b9a..9d829ac45a1 100644 --- a/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp +++ b/lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp @@ -48,9 +48,6 @@ public: return false; } - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override {} - bool writeNopData(raw_ostream &OS, uint64_t Count) const override; }; diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index bc537bcc4c4..e7069819fa5 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -651,11 +651,12 @@ public: llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced"); } - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override { + void relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const override { assert(HexagonMCInstrInfo::isBundle(Inst) && "Hexagon relaxInstruction only works on bundles"); + MCInst Res; Res.setOpcode(Hexagon::BUNDLE); Res.addOperand(MCOperand::createImm(Inst.getOperand(0).getImm())); // Copy the results into the bundle. @@ -679,6 +680,8 @@ public: // now copy over the original instruction(the one we may have extended) Res.addOperand(MCOperand::createInst(I.getInst())); } + + Inst = std::move(Res); (void)Update; assert(Update && "Didn't find relaxation target"); } diff --git a/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp b/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp index a6ce3d5eb4f..0fb27a92600 100644 --- a/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp +++ b/lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp @@ -74,10 +74,6 @@ public: return false; } - void relaxInstruction(const MCInst & /*Inst*/, - const MCSubtargetInfo & /*STI*/, - MCInst & /*Res*/) const override {} - bool writeNopData(raw_ostream &OS, uint64_t Count) const override; }; diff --git a/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp b/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp index 365e5da74de..958212dc77c 100644 --- a/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp +++ b/lib/Target/MSP430/MCTargetDesc/MSP430AsmBackend.cpp @@ -95,9 +95,6 @@ public: return false; } - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override {} - bool writeNopData(raw_ostream &OS, uint64_t Count) const override; }; diff --git a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h index cca75dfc45c..7b55d66fdc3 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h +++ b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h @@ -74,17 +74,6 @@ public: return false; } - /// RelaxInstruction - Relax the instruction in the given fragment - /// to the next wider instruction. - /// - /// \param Inst - The instruction to relax, which may be the same - /// as the output. - /// \param [out] Res On return, the relaxed instruction. - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override {} - - /// @} - bool writeNopData(raw_ostream &OS, uint64_t Count) const override; bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp index 0a7d5355dcb..dbaf221db9f 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -192,8 +192,8 @@ public: llvm_unreachable("relaxInstruction() unimplemented"); } - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override { + void relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const override { // FIXME. llvm_unreachable("relaxInstruction() unimplemented"); } diff --git a/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp index 6e9685ef9c1..bb1f1cc7f49 100644 --- a/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -139,10 +139,10 @@ bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, } } -void RISCVAsmBackend::relaxInstruction(const MCInst &Inst, - const MCSubtargetInfo &STI, - MCInst &Res) const { +void RISCVAsmBackend::relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const { // TODO: replace this with call to auto generated uncompressinstr() function. + MCInst Res; switch (Inst.getOpcode()) { default: llvm_unreachable("Opcode not expected!"); @@ -173,6 +173,7 @@ void RISCVAsmBackend::relaxInstruction(const MCInst &Inst, Res.addOperand(Inst.getOperand(0)); break; } + Inst = std::move(Res); } // Given a compressed control flow instruction this function returns diff --git a/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h b/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h index 92fa26c3f43..090132af358 100644 --- a/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h +++ b/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h @@ -105,9 +105,8 @@ public: const MCSubtargetInfo &STI) const override; unsigned getRelaxedOpcode(unsigned Op) const; - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override; - + void relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const override; bool writeNopData(raw_ostream &OS, uint64_t Count) const override; diff --git a/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp b/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp index 76ff446e892..83c44e0682c 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp @@ -271,8 +271,8 @@ namespace { llvm_unreachable("fixupNeedsRelaxation() unimplemented"); return false; } - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override { + void relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const override { // FIXME. llvm_unreachable("relaxInstruction() unimplemented"); } diff --git a/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp b/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp index 23d8585095c..e62f5040898 100644 --- a/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp +++ b/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp @@ -63,10 +63,6 @@ public: const MCAsmLayout &Layout) const override { return false; } - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override { - llvm_unreachable("SystemZ does do not have assembler relaxation"); - } bool writeNopData(raw_ostream &OS, uint64_t Count) const override; std::unique_ptr createObjectTargetWriter() const override { diff --git a/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp b/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp index 8314de41021..0992a3feaa4 100644 --- a/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp +++ b/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyAsmBackend.cpp @@ -64,9 +64,6 @@ public: return false; } - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override {} - bool writeNopData(raw_ostream &OS, uint64_t Count) const override; }; diff --git a/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp b/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp index a7ed81dee6d..7af29998395 100644 --- a/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp +++ b/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp @@ -192,8 +192,8 @@ public: const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const override; - void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, - MCInst &Res) const override; + void relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const override; bool padInstructionViaRelaxation(MCRelaxableFragment &RF, MCCodeEmitter &Emitter, @@ -825,9 +825,8 @@ bool X86AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, // FIXME: Can tblgen help at all here to verify there aren't other instructions // we can relax? -void X86AsmBackend::relaxInstruction(const MCInst &Inst, - const MCSubtargetInfo &STI, - MCInst &Res) const { +void X86AsmBackend::relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const { // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel. bool Is16BitMode = STI.getFeatureBits()[X86::Mode16Bit]; unsigned RelaxedOp = getRelaxedOpcode(Inst, Is16BitMode); @@ -840,8 +839,7 @@ void X86AsmBackend::relaxInstruction(const MCInst &Inst, report_fatal_error("unexpected instruction to relax: " + OS.str()); } - Res = Inst; - Res.setOpcode(RelaxedOp); + Inst.setOpcode(RelaxedOp); } /// Return true if this instruction has been fully relaxed into it's most @@ -915,8 +913,8 @@ bool X86AsmBackend::padInstructionViaRelaxation(MCRelaxableFragment &RF, // encoding size without impacting performance. return false; - MCInst Relaxed; - relaxInstruction(RF.getInst(), *RF.getSubtargetInfo(), Relaxed); + MCInst Relaxed = RF.getInst(); + relaxInstruction(Relaxed, *RF.getSubtargetInfo()); SmallVector Fixups; SmallString<15> Code; diff --git a/test/MC/RISCV/rv64-relax-all.s b/test/MC/RISCV/rv64-relax-all.s new file mode 100644 index 00000000000..5d6d74b882c --- /dev/null +++ b/test/MC/RISCV/rv64-relax-all.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c %s | llvm-objdump -d -M no-aliases --no-show-raw-insn - | FileCheck %s --check-prefix=INSTR + +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c %s --mc-relax-all | llvm-objdump -d -M no-aliases --no-show-raw-insn - | FileCheck %s --check-prefix=RELAX-INSTR + +## Check the instructions are relaxed correctly + +NEAR: + +# INSTR: c.beqz a0, 0 +# RELAX-INSTR: beq a0, zero, 0 +c.beqz a0, NEAR + +# INSTR: c.j -2 +# RELAX-INSTR: jal zero, -4 +c.j NEAR