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[PowerPC] Implement the 128-bit Vector Divide Extended Builtins in Clang/LLVM

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This patch implements the 128-bit vector divide extended builtins in Clang/LLVM.
These builtins map to the vdivesq and vdiveuq instructions respectively.

Differential Revision: https://reviews.llvm.org/D87729
This commit is contained in:
Amy Kwan 2020-09-22 09:40:45 -05:00
parent 024914484d
commit 8864893cb8
3 changed files with 31 additions and 2 deletions
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2
include/llvm/IR/IntrinsicsPowerPC.td
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@ -1007,6 +1007,8 @@ def int_ppc_altivec_vdivesw : PowerPC_Vec_WWW_Intrinsic<"vdivesw">;
def int_ppc_altivec_vdiveuw : PowerPC_Vec_WWW_Intrinsic<"vdiveuw">;
def int_ppc_altivec_vdivesd : PowerPC_Vec_DDD_Intrinsic<"vdivesd">;
def int_ppc_altivec_vdiveud : PowerPC_Vec_DDD_Intrinsic<"vdiveud">;
def int_ppc_altivec_vdivesq : PowerPC_Vec_QQQ_Intrinsic<"vdivesq">;
def int_ppc_altivec_vdiveuq : PowerPC_Vec_QQQ_Intrinsic<"vdiveuq">;
// Vector Multiply High Intrinsics.
def int_ppc_altivec_vmulhsw : PowerPC_Vec_WWW_Intrinsic<"vmulhsw">;

8
lib/Target/PowerPC/PPCInstrPrefix.td
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@ -1427,9 +1427,13 @@ let Predicates = [IsISA3_1] in {
"vdivuq $vD, $vA, $vB", IIC_VecGeneral,
[(set v1i128:$vD, (udiv v1i128:$vA, v1i128:$vB))]>;
def VDIVESQ : VXForm_1<779, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vdivesq $vD, $vA, $vB", IIC_VecGeneral, []>;
"vdivesq $vD, $vA, $vB", IIC_VecGeneral,
[(set v1i128:$vD, (int_ppc_altivec_vdivesq v1i128:$vA,
v1i128:$vB))]>;
def VDIVEUQ : VXForm_1<523, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vdiveuq $vD, $vA, $vB", IIC_VecGeneral, []>;
"vdiveuq $vD, $vA, $vB", IIC_VecGeneral,
[(set v1i128:$vD, (int_ppc_altivec_vdiveuq v1i128:$vA,
v1i128:$vB))]>;
def VCMPEQUQ : VCMP <455, "vcmpequq $vD, $vA, $vB" , v1i128>;
def VCMPGTSQ : VCMP <903, "vcmpgtsq $vD, $vA, $vB" , v1i128>;
def VCMPGTUQ : VCMP <647, "vcmpgtuq $vD, $vA, $vB" , v1i128>;

23
test/CodeGen/PowerPC/p10-vector-divide.ll
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@ -9,6 +9,7 @@
; This test case aims to test the vector divide instructions on Power10.
; This includes the low order and extended versions of vector divide,
; that operate on signed and unsigned words and doublewords.
; This also includes 128 bit vector divide instructions.
define <2 x i64> @test_vdivud(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vdivud:
@ -113,3 +114,25 @@ entry:
%div = tail call <2 x i64> @llvm.ppc.altivec.vdiveud(<2 x i64> %a, <2 x i64> %b)
ret <2 x i64> %div
}
declare <1 x i128> @llvm.ppc.altivec.vdivesq(<1 x i128>, <1 x i128>) nounwind readnone
declare <1 x i128> @llvm.ppc.altivec.vdiveuq(<1 x i128>, <1 x i128>) nounwind readnone
define <1 x i128> @test_vdivesq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
; CHECK-LABEL: test_vdivesq:
; CHECK: # %bb.0:
; CHECK-NEXT: vdivesq v2, v2, v3
; CHECK-NEXT: blr
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vdivesq(<1 x i128> %x, <1 x i128> %y)
ret <1 x i128> %tmp
}
define <1 x i128> @test_vdiveuq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
; CHECK-LABEL: test_vdiveuq:
; CHECK: # %bb.0:
; CHECK-NEXT: vdiveuq v2, v2, v3
; CHECK-NEXT: blr
%tmp = call <1 x i128> @llvm.ppc.altivec.vdiveuq(<1 x i128> %x, <1 x i128> %y)
ret <1 x i128> %tmp
}