From 8865ace4e107c84dc6e69a1bbadb8eb6ed6ead20 Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Wed, 27 Mar 2013 02:40:14 +0000 Subject: [PATCH] Remove the link register from the GPR classes on PowerPC. Some implementation detail in the forgotten past required the link register to be placed in the GPRC and G8RC register classes. This is just wrong on the face of it, and causes several extra intersection register classes to be generated. I found this was having evil effects on instruction scheduling, by causing the wrong register class to be consulted for register pressure decisions. No code generation changes are expected, other than some minor changes in instruction order. Seven tests in the test bucket required minor tweaks to adjust to the new normal. llvm-svn: 178114 --- lib/Target/PowerPC/PPCRegisterInfo.td | 4 ++-- test/CodeGen/PowerPC/jaggedstructs.ll | 10 +++++----- test/CodeGen/PowerPC/structsinmem.ll | 4 ++-- test/CodeGen/PowerPC/structsinregs.ll | 4 ++-- test/CodeGen/PowerPC/tls-gd.ll | 2 +- test/CodeGen/PowerPC/tls-ld-2.ll | 4 ++-- test/CodeGen/PowerPC/tls-ld.ll | 4 ++-- test/CodeGen/PowerPC/tls.ll | 2 +- 8 files changed, 17 insertions(+), 17 deletions(-) diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index c5e325545d3..aa5584ee3c7 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -172,11 +172,11 @@ def RM: SPR<512, "**ROUNDING MODE**">; // then nonvolatiles in reverse order since stmw/lmw save from rN to r31 def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12), (sequence "R%u", 30, 13), - R31, R0, R1, LR, FP)>; + R31, R0, R1, FP)>; def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12), (sequence "X%u", 30, 14), - X31, X13, X0, X1, LR8, FP8)>; + X31, X13, X0, X1, FP8)>; // For some instructions r0 is special (representing the value 0 instead of // the value in the r0 register), and we use these register subclasses to diff --git a/test/CodeGen/PowerPC/jaggedstructs.ll b/test/CodeGen/PowerPC/jaggedstructs.ll index 62aa7cf929f..a10c5ddb36f 100644 --- a/test/CodeGen/PowerPC/jaggedstructs.ll +++ b/test/CodeGen/PowerPC/jaggedstructs.ll @@ -23,22 +23,22 @@ entry: ; CHECK: std 4, 200(1) ; CHECK: std 3, 192(1) ; CHECK: lbz {{[0-9]+}}, 199(1) -; CHECK: stb {{[0-9]+}}, 55(1) ; CHECK: lhz {{[0-9]+}}, 197(1) +; CHECK: stb {{[0-9]+}}, 55(1) ; CHECK: sth {{[0-9]+}}, 53(1) ; CHECK: lbz {{[0-9]+}}, 207(1) -; CHECK: stb {{[0-9]+}}, 63(1) ; CHECK: lwz {{[0-9]+}}, 203(1) +; CHECK: stb {{[0-9]+}}, 63(1) ; CHECK: stw {{[0-9]+}}, 59(1) ; CHECK: lhz {{[0-9]+}}, 214(1) -; CHECK: sth {{[0-9]+}}, 70(1) ; CHECK: lwz {{[0-9]+}}, 210(1) +; CHECK: sth {{[0-9]+}}, 70(1) ; CHECK: stw {{[0-9]+}}, 66(1) ; CHECK: lbz {{[0-9]+}}, 223(1) -; CHECK: stb {{[0-9]+}}, 79(1) ; CHECK: lhz {{[0-9]+}}, 221(1) -; CHECK: sth {{[0-9]+}}, 77(1) ; CHECK: lwz {{[0-9]+}}, 217(1) +; CHECK: stb {{[0-9]+}}, 79(1) +; CHECK: sth {{[0-9]+}}, 77(1) ; CHECK: stw {{[0-9]+}}, 73(1) ; CHECK: ld 6, 72(1) ; CHECK: ld 5, 64(1) diff --git a/test/CodeGen/PowerPC/structsinmem.ll b/test/CodeGen/PowerPC/structsinmem.ll index 8dbe63dc726..2a17e740ea0 100644 --- a/test/CodeGen/PowerPC/structsinmem.ll +++ b/test/CodeGen/PowerPC/structsinmem.ll @@ -114,8 +114,8 @@ entry: ret i32 %add13 ; CHECK: lha {{[0-9]+}}, 126(1) -; CHECK: lbz {{[0-9]+}}, 119(1) ; CHECK: lha {{[0-9]+}}, 132(1) +; CHECK: lbz {{[0-9]+}}, 119(1) ; CHECK: lwz {{[0-9]+}}, 140(1) ; CHECK: lwz {{[0-9]+}}, 144(1) ; CHECK: lwz {{[0-9]+}}, 152(1) @@ -206,8 +206,8 @@ entry: ret i32 %add13 ; CHECK: lha {{[0-9]+}}, 126(1) -; CHECK: lbz {{[0-9]+}}, 119(1) ; CHECK: lha {{[0-9]+}}, 133(1) +; CHECK: lbz {{[0-9]+}}, 119(1) ; CHECK: lwz {{[0-9]+}}, 140(1) ; CHECK: lwz {{[0-9]+}}, 147(1) ; CHECK: lwz {{[0-9]+}}, 154(1) diff --git a/test/CodeGen/PowerPC/structsinregs.ll b/test/CodeGen/PowerPC/structsinregs.ll index 6005614bdda..54de6060d0f 100644 --- a/test/CodeGen/PowerPC/structsinregs.ll +++ b/test/CodeGen/PowerPC/structsinregs.ll @@ -105,8 +105,8 @@ entry: ; CHECK: sth 4, 62(1) ; CHECK: stb 3, 55(1) ; CHECK: lha {{[0-9]+}}, 62(1) -; CHECK: lbz {{[0-9]+}}, 55(1) ; CHECK: lha {{[0-9]+}}, 68(1) +; CHECK: lbz {{[0-9]+}}, 55(1) ; CHECK: lwz {{[0-9]+}}, 76(1) ; CHECK: lwz {{[0-9]+}}, 80(1) ; CHECK: lwz {{[0-9]+}}, 88(1) @@ -192,8 +192,8 @@ entry: ; CHECK: sth 4, 62(1) ; CHECK: stb 3, 55(1) ; CHECK: lha {{[0-9]+}}, 62(1) -; CHECK: lbz {{[0-9]+}}, 55(1) ; CHECK: lha {{[0-9]+}}, 69(1) +; CHECK: lbz {{[0-9]+}}, 55(1) ; CHECK: lwz {{[0-9]+}}, 76(1) ; CHECK: lwz {{[0-9]+}}, 83(1) ; CHECK: lwz {{[0-9]+}}, 90(1) diff --git a/test/CodeGen/PowerPC/tls-gd.ll b/test/CodeGen/PowerPC/tls-gd.ll index fb8dfaf04a9..5f0ef9a050d 100644 --- a/test/CodeGen/PowerPC/tls-gd.ll +++ b/test/CodeGen/PowerPC/tls-gd.ll @@ -18,6 +18,6 @@ entry: ; CHECK: addis [[REG:[0-9]+]], 2, a@got@tlsgd@ha ; CHECK-NEXT: addi 3, [[REG]], a@got@tlsgd@l -; CHECK-NEXT: bl __tls_get_addr(a@tlsgd) +; CHECK: bl __tls_get_addr(a@tlsgd) ; CHECK-NEXT: nop diff --git a/test/CodeGen/PowerPC/tls-ld-2.ll b/test/CodeGen/PowerPC/tls-ld-2.ll index 4954afeb24f..4399b330ea4 100644 --- a/test/CodeGen/PowerPC/tls-ld-2.ll +++ b/test/CodeGen/PowerPC/tls-ld-2.ll @@ -18,7 +18,7 @@ entry: ; CHECK: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha ; CHECK-NEXT: addi 3, [[REG]], a@got@tlsld@l -; CHECK-NEXT: bl __tls_get_addr(a@tlsld) +; CHECK: bl __tls_get_addr(a@tlsld) ; CHECK-NEXT: nop -; CHECK-NEXT: addis [[REG2:[0-9]+]], 3, a@dtprel@ha +; CHECK: addis [[REG2:[0-9]+]], 3, a@dtprel@ha ; CHECK-NEXT: lwa {{[0-9]+}}, a@dtprel@l([[REG2]]) diff --git a/test/CodeGen/PowerPC/tls-ld.ll b/test/CodeGen/PowerPC/tls-ld.ll index 1ebc6129e2a..db02a56f6a2 100644 --- a/test/CodeGen/PowerPC/tls-ld.ll +++ b/test/CodeGen/PowerPC/tls-ld.ll @@ -18,7 +18,7 @@ entry: ; CHECK: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha ; CHECK-NEXT: addi 3, [[REG]], a@got@tlsld@l -; CHECK-NEXT: bl __tls_get_addr(a@tlsld) +; CHECK: bl __tls_get_addr(a@tlsld) ; CHECK-NEXT: nop -; CHECK-NEXT: addis [[REG2:[0-9]+]], 3, a@dtprel@ha +; CHECK: addis [[REG2:[0-9]+]], 3, a@dtprel@ha ; CHECK-NEXT: addi {{[0-9]+}}, [[REG2]], a@dtprel@l diff --git a/test/CodeGen/PowerPC/tls.ll b/test/CodeGen/PowerPC/tls.ll index 151b4b7ddab..2daa60ab37f 100644 --- a/test/CodeGen/PowerPC/tls.ll +++ b/test/CodeGen/PowerPC/tls.ll @@ -12,7 +12,7 @@ entry: ;OPT0: addis [[REG1:[0-9]+]], 13, a@tprel@ha ;OPT0-NEXT: li [[REG2:[0-9]+]], 42 ;OPT0-NEXT: addi [[REG1]], [[REG1]], a@tprel@l -;OPT0-NEXT: stw [[REG2]], 0([[REG1]]) +;OPT0: stw [[REG2]], 0([[REG1]]) ;OPT1: addis [[REG1:[0-9]+]], 13, a@tprel@ha ;OPT1-NEXT: li [[REG2:[0-9]+]], 42 ;OPT1-NEXT: stw [[REG2]], a@tprel@l([[REG1]])