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AMDGPU/GlobalISel/Emitter Recognize additional 'same operand checks'
The "name" of a non-leaf complex pattern (MY_PAT $op1, $op2) is "MY_PAT:op1:op2" and the ones with same "name" represent same operand. Add 'same operand check' for this case. Differential Revision: https://reviews.llvm.org/D87351
This commit is contained in:
Petar Avramovic
parent
c5275c6e58
commit
8865fe468c
@ -25,8 +25,7 @@ body: |
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; CHECK: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
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; CHECK: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[S_LOAD_DWORDX2_IMM]]
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; CHECK: %12:vreg_64 = nofpexcept V_ADD_F64 0, [[COPY3]], 1, [[COPY4]], 0, 0, implicit $mode, implicit $exec
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; CHECK: %13:vreg_64 = nofpexcept V_FLOOR_F64_e64 0, %12, 0, 0, implicit $mode, implicit $exec
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; CHECK: %15:vreg_64 = nofpexcept V_ADD_F64 0, %12, 1, %13, 0, 0, implicit $mode, implicit $exec
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; CHECK: %15:vreg_64 = nofpexcept V_FRACT_F64_e64 0, %12, 0, 0, implicit $mode, implicit $exec
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; CHECK: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
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; CHECK: GLOBAL_STORE_DWORDX2 [[COPY5]], %15, 0, 0, 0, 0, implicit $exec :: (store 8, addrspace 1)
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; CHECK: S_ENDPGM 0
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@ -76,8 +75,7 @@ body: |
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; CHECK: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
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; CHECK: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[S_LOAD_DWORDX2_IMM]]
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; CHECK: %13:vreg_64 = nofpexcept V_ADD_F64 0, [[COPY3]], 3, [[COPY4]], 0, 0, implicit $mode, implicit $exec
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; CHECK: %14:vreg_64 = nofpexcept V_FLOOR_F64_e64 0, %13, 0, 0, implicit $mode, implicit $exec
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; CHECK: %16:vreg_64 = nofpexcept V_ADD_F64 0, %13, 1, %14, 0, 0, implicit $mode, implicit $exec
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; CHECK: %16:vreg_64 = nofpexcept V_FRACT_F64_e64 0, %13, 0, 0, implicit $mode, implicit $exec
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; CHECK: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
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; CHECK: GLOBAL_STORE_DWORDX2 [[COPY5]], %16, 0, 0, 0, 0, implicit $exec :: (store 8, addrspace 1)
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; CHECK: S_ENDPGM 0
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@ -255,7 +255,7 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
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// R19N-NEXT: // MIs[0] src1
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// R19N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
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// R19N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
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// R19N-NEXT: // MIs[0] Operand 2
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// R19N-NEXT: // MIs[0] complex_rr:src2a:src2b
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// R19N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
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//
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// R19N-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_complex_rr,
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@ -274,7 +274,7 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; }
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// R19N-NEXT: // MIs[1] src4
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// R19N-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
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// R19N-NEXT: GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/1, GICP_gi_complex,
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// R19N-NEXT: // MIs[1] Operand 3
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// R19N-NEXT: // MIs[1] complex:src5a:src5b
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// R19N-NEXT: GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
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// R19N-NEXT: GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/2, GICP_gi_complex,
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// R19O-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
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@ -23,7 +23,7 @@ def INSN : I<(outs GPR32:$dst), (ins GPR32:$src1, complex:$src2), []>;
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//===- Bail out when we define a variable twice wrt complex suboperands. -===//
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// CHECK: warning: Skipped pattern: Complex suboperand referenced more than once (Operand: x)
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// CHECK: warning: Skipped pattern: Error: Complex suboperand x referenced by different operands: complex_rr:x:y and complex_rr:x:z.
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def : Pat<(add (complex_rr GPR32:$x, GPR32:$y),
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(complex_rr GPR32:$x, GPR32:$z)),
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(INSN GPR32:$z, complex:$y)>;
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@ -856,6 +856,11 @@ protected:
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DefinedComplexPatternSubOperandMap;
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/// A map of Symbolic Names to ComplexPattern sub-operands.
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DefinedComplexPatternSubOperandMap ComplexSubOperands;
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/// A map used to for multiple referenced error check of ComplexSubOperand.
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/// ComplexSubOperand can't be referenced multiple from different operands,
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/// however multiple references from same operand are allowed since that is
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/// how 'same operand checks' are generated.
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StringMap<std::string> ComplexSubOperandsParentName;
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uint64_t RuleID;
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static uint64_t NextRuleID;
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@ -921,14 +926,24 @@ public:
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void definePhysRegOperand(Record *Reg, OperandMatcher &OM);
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Error defineComplexSubOperand(StringRef SymbolicName, Record *ComplexPattern,
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unsigned RendererID, unsigned SubOperandID) {
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if (ComplexSubOperands.count(SymbolicName))
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return failedImport(
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"Complex suboperand referenced more than once (Operand: " +
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SymbolicName + ")");
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unsigned RendererID, unsigned SubOperandID,
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StringRef ParentSymbolicName) {
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std::string ParentName(ParentSymbolicName);
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if (ComplexSubOperands.count(SymbolicName)) {
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auto RecordedParentName = ComplexSubOperandsParentName[SymbolicName];
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if (RecordedParentName.compare(ParentName) != 0)
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return failedImport("Error: Complex suboperand " + SymbolicName +
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" referenced by different operands: " +
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RecordedParentName + " and " + ParentName + ".");
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// Complex suboperand referenced more than once from same the operand is
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// used to generate 'same operand check'. Emitting of
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// GIR_ComplexSubOperandRenderer for them is already handled.
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return Error::success();
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}
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ComplexSubOperands[SymbolicName] =
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std::make_tuple(ComplexPattern, RendererID, SubOperandID);
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ComplexSubOperandsParentName[SymbolicName] = ParentName;
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return Error::success();
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}
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@ -4100,12 +4115,22 @@ Error GlobalISelEmitter::importChildMatcher(
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bool OperandIsImmArg, unsigned OpIdx, unsigned &TempOpIdx) {
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Record *PhysReg = nullptr;
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StringRef SrcChildName = getSrcChildName(SrcChild, PhysReg);
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std::string SrcChildName = std::string(getSrcChildName(SrcChild, PhysReg));
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if (!SrcChild->isLeaf() &&
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SrcChild->getOperator()->isSubClassOf("ComplexPattern")) {
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// The "name" of a non-leaf complex pattern (MY_PAT $op1, $op2) is
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// "MY_PAT:op1:op2" and the ones with same "name" represent same operand.
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std::string PatternName = std::string(SrcChild->getOperator()->getName());
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for (unsigned i = 0; i < SrcChild->getNumChildren(); ++i) {
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PatternName += ":";
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PatternName += SrcChild->getChild(i)->getName();
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}
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SrcChildName = PatternName;
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}
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OperandMatcher &OM =
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PhysReg
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? InsnMatcher.addPhysRegInput(PhysReg, OpIdx, TempOpIdx)
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: InsnMatcher.addOperand(OpIdx, std::string(SrcChildName), TempOpIdx);
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PhysReg ? InsnMatcher.addPhysRegInput(PhysReg, OpIdx, TempOpIdx)
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: InsnMatcher.addOperand(OpIdx, SrcChildName, TempOpIdx);
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if (OM.isSameAsAnotherOperand())
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return Error::success();
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@ -4152,9 +4177,9 @@ Error GlobalISelEmitter::importChildMatcher(
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for (unsigned i = 0, e = SrcChild->getNumChildren(); i != e; ++i) {
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auto *SubOperand = SrcChild->getChild(i);
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if (!SubOperand->getName().empty()) {
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if (auto Error = Rule.defineComplexSubOperand(SubOperand->getName(),
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SrcChild->getOperator(),
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RendererID, i))
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if (auto Error = Rule.defineComplexSubOperand(
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SubOperand->getName(), SrcChild->getOperator(), RendererID, i,
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SrcChildName))
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return Error;
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}
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}
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