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[Hexagon] Don't generate short vectors in ISD::SELECT in preprocessing

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Selection DAG preprocessing runs long after legalization, so make sure
that the types can be handled by the selection code.
This commit is contained in:
Krzysztof Parzyszek 2020-02-11 15:17:22 -06:00
parent 13cfdc2bb4
commit 886e13050e
2 changed files with 45 additions and 3 deletions
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13
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
View File

@ -1187,7 +1187,7 @@ void HexagonDAGToDAGISel::ppHoistZextI1(std::vector<SDNode*> &&Nodes) {
Ops[i] = U->getOperand(i);
EVT BVT = Ops[I1N].getValueType();
SDLoc dl(U);
const SDLoc &dl(U);
SDValue C0 = DAG.getConstant(0, dl, BVT);
SDValue C1 = DAG.getConstant(1, dl, BVT);
SDValue If0, If1;
@ -1205,8 +1205,15 @@ void HexagonDAGToDAGISel::ppHoistZextI1(std::vector<SDNode*> &&Nodes) {
Ops[I1N] = C1;
If1 = DAG.getNode(UseOpc, dl, UVT, Ops);
}
SDValue Sel = DAG.getNode(ISD::SELECT, dl, UVT, OpI1, If1, If0);
DAG.ReplaceAllUsesWith(U, Sel.getNode());
// We're generating a SELECT way after legalization, so keep the types
// simple.
unsigned UW = UVT.getSizeInBits();
EVT SVT = (UW == 32 || UW == 64) ? MVT::getIntegerVT(UW) : UVT;
SDValue Sel = DAG.getNode(ISD::SELECT, dl, SVT, OpI1,
DAG.getBitcast(SVT, If1),
DAG.getBitcast(SVT, If0));
SDValue Ret = DAG.getBitcast(UVT, Sel);
DAG.ReplaceAllUsesWith(U, Ret.getNode());
}
}
}

35
test/CodeGen/Hexagon/isel-select-v4i8.ll Normal file
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@ -0,0 +1,35 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; This used to fail:
; LLVM ERROR: Cannot select: t54: v4i8 = select t50, t53, t52
; CHECK: jumpr r31
target triple = "hexagon"
@g0 = external dso_local unnamed_addr constant [41 x i8], align 1
define dso_local void @f0() local_unnamed_addr #0 {
b0:
%v0 = load <16 x i32>, <16 x i32>* undef, align 16
%v1 = icmp eq <16 x i32> %v0, zeroinitializer
%v2 = or <16 x i1> %v1, zeroinitializer
%v3 = or <16 x i1> %v2, zeroinitializer
%v4 = or <16 x i1> %v3, zeroinitializer
%v5 = shufflevector <16 x i1> %v4, <16 x i1> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%v6 = or <16 x i1> %v4, %v5
%v7 = extractelement <16 x i1> %v6, i32 0
%v8 = or i1 %v7, undef
%v9 = or i1 %v8, undef
br i1 %v9, label %b2, label %b1
b1: ; preds = %b0
call void (i8*, ...) @f1(i8* getelementptr inbounds ([41 x i8], [41 x i8]* @g0, i32 0, i32 0))
unreachable
b2: ; preds = %b0
ret void
}
declare dso_local void @f1(i8*, ...) local_unnamed_addr #1
attributes #0 = { "target-cpu"="hexagonv66" "target-features"="+hvx-length64b,+hvxv66,+v66,-long-calls" }
attributes #1 = { "use-soft-float"="false" }