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[X86][AVX-512] Don't raise inexact in ceil, floor, round, trunc.
The non-AVX-512 behavior was changed in r248266 to match N1778
(C bindings for IEEE-754 (2008)), which defined the four functions
to not raise the inexact exception ("rint" is still defined as raising
it).
Update the AVX-512 lowering of these functions to match that: it should
not be different.
llvm-svn: 306299
This commit is contained in:
Ahmed Bougacha
parent
4e1d2d8ecf
commit
888a374555
@ -7265,13 +7265,13 @@ avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
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let Predicates = [HasAVX512] in {
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def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
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(_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;
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(_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x9))), _.FRC)>;
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def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
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(_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;
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(_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xa))), _.FRC)>;
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def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
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(_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;
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(_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xb))), _.FRC)>;
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def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),
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(_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;
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@ -7281,13 +7281,13 @@ avx512_rndscale_scalar<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
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def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
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addr:$src, (i32 0x1))), _.FRC)>;
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addr:$src, (i32 0x9))), _.FRC)>;
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def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
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addr:$src, (i32 0x2))), _.FRC)>;
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addr:$src, (i32 0xa))), _.FRC)>;
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def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
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addr:$src, (i32 0x3))), _.FRC)>;
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addr:$src, (i32 0xb))), _.FRC)>;
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def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS
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(_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),
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addr:$src, (i32 0x4))), _.FRC)>;
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@ -8471,26 +8471,26 @@ multiclass avx512_shuff_packed_128<string OpcodeStr, AVX512VLVectorVTInfo _,
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}
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let Predicates = [HasAVX512] in {
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def : Pat<(v16f32 (ffloor VR512:$src)),
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(VRNDSCALEPSZrri VR512:$src, (i32 0x1))>;
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(VRNDSCALEPSZrri VR512:$src, (i32 0x9))>;
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def : Pat<(v16f32 (fnearbyint VR512:$src)),
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(VRNDSCALEPSZrri VR512:$src, (i32 0xC))>;
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def : Pat<(v16f32 (fceil VR512:$src)),
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(VRNDSCALEPSZrri VR512:$src, (i32 0x2))>;
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(VRNDSCALEPSZrri VR512:$src, (i32 0xA))>;
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def : Pat<(v16f32 (frint VR512:$src)),
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(VRNDSCALEPSZrri VR512:$src, (i32 0x4))>;
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def : Pat<(v16f32 (ftrunc VR512:$src)),
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(VRNDSCALEPSZrri VR512:$src, (i32 0x3))>;
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(VRNDSCALEPSZrri VR512:$src, (i32 0xB))>;
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def : Pat<(v8f64 (ffloor VR512:$src)),
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(VRNDSCALEPDZrri VR512:$src, (i32 0x1))>;
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(VRNDSCALEPDZrri VR512:$src, (i32 0x9))>;
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def : Pat<(v8f64 (fnearbyint VR512:$src)),
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(VRNDSCALEPDZrri VR512:$src, (i32 0xC))>;
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def : Pat<(v8f64 (fceil VR512:$src)),
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(VRNDSCALEPDZrri VR512:$src, (i32 0x2))>;
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(VRNDSCALEPDZrri VR512:$src, (i32 0xA))>;
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def : Pat<(v8f64 (frint VR512:$src)),
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(VRNDSCALEPDZrri VR512:$src, (i32 0x4))>;
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def : Pat<(v8f64 (ftrunc VR512:$src)),
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(VRNDSCALEPDZrri VR512:$src, (i32 0x3))>;
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(VRNDSCALEPDZrri VR512:$src, (i32 0xB))>;
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}
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defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4",avx512vl_f32_info, 0x23>,
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@ -2,7 +2,7 @@
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define <16 x float> @floor_v16f32(<16 x float> %a) {
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; CHECK-LABEL: floor_v16f32
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; CHECK: vrndscaleps $1, {{.*}}encoding: [0x62,0xf3,0x7d,0x48,0x08,0xc0,0x01]
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; CHECK: vrndscaleps $9, {{.*}}encoding: [0x62,0xf3,0x7d,0x48,0x08,0xc0,0x09]
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%res = call <16 x float> @llvm.floor.v16f32(<16 x float> %a)
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ret <16 x float> %res
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}
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@ -10,7 +10,7 @@ declare <16 x float> @llvm.floor.v16f32(<16 x float> %p)
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define <8 x double> @floor_v8f64(<8 x double> %a) {
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; CHECK-LABEL: floor_v8f64
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; CHECK: vrndscalepd $1, {{.*}}encoding: [0x62,0xf3,0xfd,0x48,0x09,0xc0,0x01]
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; CHECK: vrndscalepd $9, {{.*}}encoding: [0x62,0xf3,0xfd,0x48,0x09,0xc0,0x09]
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%res = call <8 x double> @llvm.floor.v8f64(<8 x double> %a)
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ret <8 x double> %res
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}
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@ -18,7 +18,7 @@ declare <8 x double> @llvm.floor.v8f64(<8 x double> %p)
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define <16 x float> @ceil_v16f32(<16 x float> %a) {
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; CHECK-LABEL: ceil_v16f32
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; CHECK: vrndscaleps $2, {{.*}}encoding: [0x62,0xf3,0x7d,0x48,0x08,0xc0,0x02]
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; CHECK: vrndscaleps $10, {{.*}}encoding: [0x62,0xf3,0x7d,0x48,0x08,0xc0,0x0a]
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%res = call <16 x float> @llvm.ceil.v16f32(<16 x float> %a)
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ret <16 x float> %res
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}
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@ -26,7 +26,7 @@ declare <16 x float> @llvm.ceil.v16f32(<16 x float> %p)
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define <8 x double> @ceil_v8f64(<8 x double> %a) {
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; CHECK-LABEL: ceil_v8f64
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; CHECK: vrndscalepd $2, {{.*}}encoding: [0x62,0xf3,0xfd,0x48,0x09,0xc0,0x02]
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; CHECK: vrndscalepd $10, {{.*}}encoding: [0x62,0xf3,0xfd,0x48,0x09,0xc0,0x0a]
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%res = call <8 x double> @llvm.ceil.v8f64(<8 x double> %a)
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ret <8 x double> %res
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}
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@ -34,7 +34,7 @@ declare <8 x double> @llvm.ceil.v8f64(<8 x double> %p)
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define <16 x float> @trunc_v16f32(<16 x float> %a) {
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; CHECK-LABEL: trunc_v16f32
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; CHECK: vrndscaleps $3, {{.*}}encoding: [0x62,0xf3,0x7d,0x48,0x08,0xc0,0x03]
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; CHECK: vrndscaleps $11, {{.*}}encoding: [0x62,0xf3,0x7d,0x48,0x08,0xc0,0x0b]
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%res = call <16 x float> @llvm.trunc.v16f32(<16 x float> %a)
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ret <16 x float> %res
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}
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@ -42,7 +42,7 @@ declare <16 x float> @llvm.trunc.v16f32(<16 x float> %p)
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define <8 x double> @trunc_v8f64(<8 x double> %a) {
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; CHECK-LABEL: trunc_v8f64
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; CHECK: vrndscalepd $3, {{.*}}encoding: [0x62,0xf3,0xfd,0x48,0x09,0xc0,0x03]
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; CHECK: vrndscalepd $11, {{.*}}encoding: [0x62,0xf3,0xfd,0x48,0x09,0xc0,0x0b]
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%res = call <8 x double> @llvm.trunc.v8f64(<8 x double> %a)
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ret <8 x double> %res
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}
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@ -90,7 +90,7 @@ declare double @llvm.nearbyint.f64(double %p)
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define float @floor_f32(float %a) {
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; CHECK-LABEL: floor_f32
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; CHECK: vrndscaless $1, {{.*}}encoding: [0x62,0xf3,0x7d,0x08,0x0a,0xc0,0x01]
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; CHECK: vrndscaless $9, {{.*}}encoding: [0x62,0xf3,0x7d,0x08,0x0a,0xc0,0x09]
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%res = call float @llvm.floor.f32(float %a)
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ret float %res
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}
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@ -98,7 +98,7 @@ declare float @llvm.floor.f32(float %p)
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define float @floor_f32m(float* %aptr) {
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; CHECK-LABEL: floor_f32m
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; CHECK: vrndscaless $1, (%rdi), {{.*}}encoding: [0x62,0xf3,0x7d,0x08,0x0a,0x07,0x01]
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; CHECK: vrndscaless $9, (%rdi), {{.*}}encoding: [0x62,0xf3,0x7d,0x08,0x0a,0x07,0x09]
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%a = load float, float* %aptr, align 4
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%res = call float @llvm.floor.f32(float %a)
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ret float %res
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