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Add DWARF numbers of 64-bit registers.

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llvm-svn: 149583
This commit is contained in:
Akira Hatanaka 2012-02-02 02:56:14 +00:00
parent 47bfe93819
commit 88e74ead4b
1 changed files with 64 additions and 64 deletions
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128
lib/Target/Mips/MipsRegisterInfo.td
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@ -106,38 +106,38 @@ let Namespace = "Mips" in {
def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>;
// General Purpose 64-bit Registers
def ZERO_64 : Mips64GPRReg< 0, "ZERO", [ZERO]>;
def AT_64 : Mips64GPRReg< 1, "AT", [AT]>;
def V0_64 : Mips64GPRReg< 2, "2", [V0]>;
def V1_64 : Mips64GPRReg< 3, "3", [V1]>;
def A0_64 : Mips64GPRReg< 4, "4", [A0]>;
def A1_64 : Mips64GPRReg< 5, "5", [A1]>;
def A2_64 : Mips64GPRReg< 6, "6", [A2]>;
def A3_64 : Mips64GPRReg< 7, "7", [A3]>;
def T0_64 : Mips64GPRReg< 8, "8", [T0]>;
def T1_64 : Mips64GPRReg< 9, "9", [T1]>;
def T2_64 : Mips64GPRReg< 10, "10", [T2]>;
def T3_64 : Mips64GPRReg< 11, "11", [T3]>;
def T4_64 : Mips64GPRReg< 12, "12", [T4]>;
def T5_64 : Mips64GPRReg< 13, "13", [T5]>;
def T6_64 : Mips64GPRReg< 14, "14", [T6]>;
def T7_64 : Mips64GPRReg< 15, "15", [T7]>;
def S0_64 : Mips64GPRReg< 16, "16", [S0]>;
def S1_64 : Mips64GPRReg< 17, "17", [S1]>;
def S2_64 : Mips64GPRReg< 18, "18", [S2]>;
def S3_64 : Mips64GPRReg< 19, "19", [S3]>;
def S4_64 : Mips64GPRReg< 20, "20", [S4]>;
def S5_64 : Mips64GPRReg< 21, "21", [S5]>;
def S6_64 : Mips64GPRReg< 22, "22", [S6]>;
def S7_64 : Mips64GPRReg< 23, "23", [S7]>;
def T8_64 : Mips64GPRReg< 24, "24", [T8]>;
def T9_64 : Mips64GPRReg< 25, "25", [T9]>;
def K0_64 : Mips64GPRReg< 26, "26", [K0]>;
def K1_64 : Mips64GPRReg< 27, "27", [K1]>;
def GP_64 : Mips64GPRReg< 28, "GP", [GP]>;
def SP_64 : Mips64GPRReg< 29, "SP", [SP]>;
def FP_64 : Mips64GPRReg< 30, "FP", [FP]>;
def RA_64 : Mips64GPRReg< 31, "RA", [RA]>;
def ZERO_64 : Mips64GPRReg< 0, "ZERO", [ZERO]>, DwarfRegNum<[0]>;
def AT_64 : Mips64GPRReg< 1, "AT", [AT]>, DwarfRegNum<[1]>;
def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>;
def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>;
def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>;
def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>;
def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>;
def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>;
def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>;
def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>;
def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>;
def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>;
def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>;
def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>;
def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>;
def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>;
def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>;
def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>;
def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>;
def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>;
def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>;
def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>;
def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>;
def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>;
def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>;
def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>;
def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>;
def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>;
def GP_64 : Mips64GPRReg< 28, "GP", [GP]>, DwarfRegNum<[28]>;
def SP_64 : Mips64GPRReg< 29, "SP", [SP]>, DwarfRegNum<[29]>;
def FP_64 : Mips64GPRReg< 30, "FP", [FP]>, DwarfRegNum<[30]>;
def RA_64 : Mips64GPRReg< 31, "RA", [RA]>, DwarfRegNum<[31]>;
/// Mips Single point precision FPU Registers
def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;
@ -193,38 +193,38 @@ let Namespace = "Mips" in {
def D15 : AFPR<30, "F30", [F30, F31]>;
/// Mips Double point precision FPU Registers in MFP64 mode.
def D0_64 : AFPR64<0, "F0", [F0]>;
def D1_64 : AFPR64<1, "F1", [F1]>;
def D2_64 : AFPR64<2, "F2", [F2]>;
def D3_64 : AFPR64<3, "F3", [F3]>;
def D4_64 : AFPR64<4, "F4", [F4]>;
def D5_64 : AFPR64<5, "F5", [F5]>;
def D6_64 : AFPR64<6, "F6", [F6]>;
def D7_64 : AFPR64<7, "F7", [F7]>;
def D8_64 : AFPR64<8, "F8", [F8]>;
def D9_64 : AFPR64<9, "F9", [F9]>;
def D10_64 : AFPR64<10, "F10", [F10]>;
def D11_64 : AFPR64<11, "F11", [F11]>;
def D12_64 : AFPR64<12, "F12", [F12]>;
def D13_64 : AFPR64<13, "F13", [F13]>;
def D14_64 : AFPR64<14, "F14", [F14]>;
def D15_64 : AFPR64<15, "F15", [F15]>;
def D16_64 : AFPR64<16, "F16", [F16]>;
def D17_64 : AFPR64<17, "F17", [F17]>;
def D18_64 : AFPR64<18, "F18", [F18]>;
def D19_64 : AFPR64<19, "F19", [F19]>;
def D20_64 : AFPR64<20, "F20", [F20]>;
def D21_64 : AFPR64<21, "F21", [F21]>;
def D22_64 : AFPR64<22, "F22", [F22]>;
def D23_64 : AFPR64<23, "F23", [F23]>;
def D24_64 : AFPR64<24, "F24", [F24]>;
def D25_64 : AFPR64<25, "F25", [F25]>;
def D26_64 : AFPR64<26, "F26", [F26]>;
def D27_64 : AFPR64<27, "F27", [F27]>;
def D28_64 : AFPR64<28, "F28", [F28]>;
def D29_64 : AFPR64<29, "F29", [F29]>;
def D30_64 : AFPR64<30, "F30", [F30]>;
def D31_64 : AFPR64<31, "F31", [F31]>;
def D0_64 : AFPR64<0, "F0", [F0]>, DwarfRegNum<[32]>;
def D1_64 : AFPR64<1, "F1", [F1]>, DwarfRegNum<[33]>;
def D2_64 : AFPR64<2, "F2", [F2]>, DwarfRegNum<[34]>;
def D3_64 : AFPR64<3, "F3", [F3]>, DwarfRegNum<[35]>;
def D4_64 : AFPR64<4, "F4", [F4]>, DwarfRegNum<[36]>;
def D5_64 : AFPR64<5, "F5", [F5]>, DwarfRegNum<[37]>;
def D6_64 : AFPR64<6, "F6", [F6]>, DwarfRegNum<[38]>;
def D7_64 : AFPR64<7, "F7", [F7]>, DwarfRegNum<[39]>;
def D8_64 : AFPR64<8, "F8", [F8]>, DwarfRegNum<[40]>;
def D9_64 : AFPR64<9, "F9", [F9]>, DwarfRegNum<[41]>;
def D10_64 : AFPR64<10, "F10", [F10]>, DwarfRegNum<[42]>;
def D11_64 : AFPR64<11, "F11", [F11]>, DwarfRegNum<[43]>;
def D12_64 : AFPR64<12, "F12", [F12]>, DwarfRegNum<[44]>;
def D13_64 : AFPR64<13, "F13", [F13]>, DwarfRegNum<[45]>;
def D14_64 : AFPR64<14, "F14", [F14]>, DwarfRegNum<[46]>;
def D15_64 : AFPR64<15, "F15", [F15]>, DwarfRegNum<[47]>;
def D16_64 : AFPR64<16, "F16", [F16]>, DwarfRegNum<[48]>;
def D17_64 : AFPR64<17, "F17", [F17]>, DwarfRegNum<[49]>;
def D18_64 : AFPR64<18, "F18", [F18]>, DwarfRegNum<[50]>;
def D19_64 : AFPR64<19, "F19", [F19]>, DwarfRegNum<[51]>;
def D20_64 : AFPR64<20, "F20", [F20]>, DwarfRegNum<[52]>;
def D21_64 : AFPR64<21, "F21", [F21]>, DwarfRegNum<[53]>;
def D22_64 : AFPR64<22, "F22", [F22]>, DwarfRegNum<[54]>;
def D23_64 : AFPR64<23, "F23", [F23]>, DwarfRegNum<[55]>;
def D24_64 : AFPR64<24, "F24", [F24]>, DwarfRegNum<[56]>;
def D25_64 : AFPR64<25, "F25", [F25]>, DwarfRegNum<[57]>;
def D26_64 : AFPR64<26, "F26", [F26]>, DwarfRegNum<[58]>;
def D27_64 : AFPR64<27, "F27", [F27]>, DwarfRegNum<[59]>;
def D28_64 : AFPR64<28, "F28", [F28]>, DwarfRegNum<[60]>;
def D29_64 : AFPR64<29, "F29", [F29]>, DwarfRegNum<[61]>;
def D30_64 : AFPR64<30, "F30", [F30]>, DwarfRegNum<[62]>;
def D31_64 : AFPR64<31, "F31", [F31]>, DwarfRegNum<[63]>;
// Hi/Lo registers
def HI : Register<"hi">, DwarfRegNum<[64]>;