From 8935624e7593a84caf679bf8fe03363b9e5f4747 Mon Sep 17 00:00:00 2001
From: Evandro Menezes <e.menezes@samsung.com>
Date: Thu, 15 Mar 2018 20:31:25 +0000
Subject: [PATCH] [AArch64] Adjust the cost model for Exynos M3

Add special case for rotate right.

llvm-svn: 327662
---
 lib/Target/AArch64/AArch64SchedExynosM3.td | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/lib/Target/AArch64/AArch64SchedExynosM3.td b/lib/Target/AArch64/AArch64SchedExynosM3.td
index 2ee8be3b684..1b89ea62d1c 100644
--- a/lib/Target/AArch64/AArch64SchedExynosM3.td
+++ b/lib/Target/AArch64/AArch64SchedExynosM3.td
@@ -110,6 +110,10 @@ def M3BranchLinkFastPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
                                             MI->getOperand(0).isReg() &&
                                             MI->getOperand(0).getReg() != AArch64::LR}]>;
 def M3ResetFastPred      : SchedPredicate<[{TII->isExynosResetFast(*MI)}]>;
+def M3RotateFastPred     : SchedPredicate<[{(MI->getOpcode() == AArch64::EXTRWrri ||
+                                             MI->getOpcode() == AArch64::EXTRXrri) &&
+                                            MI->getOperand(0).isReg() && MI->getOperand(1).isReg() &&
+                                            MI->getOperand(0).getReg() == MI->getOperand(1).getReg()}]>;
 def M3ShiftLeftFastPred  : SchedPredicate<[{TII->isExynosShiftLeftFast(*MI)}]>;
 
 //===----------------------------------------------------------------------===//
@@ -136,6 +140,8 @@ def M3WriteC2 : SchedWriteRes<[M3UnitC]>   { let Latency = 2; }
 def M3WriteAX : SchedWriteVariant<[SchedVar<M3ResetFastPred,     [M3WriteZ0]>,
                                    SchedVar<M3ShiftLeftFastPred, [M3WriteA1]>,
                                    SchedVar<NoSchedPred,         [M3WriteAA]>]>;
+def M3WriteAY : SchedWriteVariant<[SchedVar<M3RotateFastPred,    [M3WriteA1]>,
+                                   SchedVar<NoSchedPred,         [M3WriteAA]>]>;
 
 def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
 def M3WriteBX : SchedWriteVariant<[SchedVar<M3BranchLinkFastPred, [M3WriteAB]>,
@@ -500,6 +506,7 @@ def : InstRW<[M3WriteZ0], (instregex "^MOV[NZ][WX]i")>;
 // Divide and multiply instructions.
 
 // Miscellaneous instructions.
+def : InstRW<[M3WriteAY], (instregex "^EXTR[WX]rri")>;
 
 // Load instructions.
 def : InstRW<[M3WriteLD,