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[AArch64] AsmParser should be case insensitive about accepting vector register names.
Differential Revision: http://reviews.llvm.org/D10320 llvm-svn: 239353
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@ -1764,7 +1764,7 @@ static unsigned MatchRegisterName(StringRef Name);
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/// }
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/// }
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static unsigned matchVectorRegName(StringRef Name) {
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static unsigned matchVectorRegName(StringRef Name) {
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return StringSwitch<unsigned>(Name)
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return StringSwitch<unsigned>(Name.lower())
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.Case("v0", AArch64::Q0)
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.Case("v0", AArch64::Q0)
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.Case("v1", AArch64::Q1)
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.Case("v1", AArch64::Q1)
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.Case("v2", AArch64::Q2)
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.Case("v2", AArch64::Q2)
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8
test/MC/AArch64/case-insen-reg-names.s
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8
test/MC/AArch64/case-insen-reg-names.s
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@ -0,0 +1,8 @@
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// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s
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fadd v0.2d, v5.2d, v6.2d
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fadd V0.2d, V5.2d, V6.2d
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fadd v0.2d, V5.2d, v6.2d
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// CHECK: fadd v0.2d, v5.2d, v6.2d // encoding: [0xa0,0xd4,0x66,0x4e]
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// CHECK: fadd v0.2d, v5.2d, v6.2d // encoding: [0xa0,0xd4,0x66,0x4e]
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// CHECK: fadd v0.2d, v5.2d, v6.2d // encoding: [0xa0,0xd4,0x66,0x4e]
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