From 8947edbd5987cf5bb040b91b5a935c4565edb32c Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 17 Apr 2017 01:51:24 +0000 Subject: [PATCH] [InstCombine] Add support for vector srem->urem. llvm-svn: 300437 --- lib/Transforms/InstCombine/InstCombineMulDivRem.cpp | 12 +++++------- test/Transforms/InstCombine/rem.ll | 2 +- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp index de0c2a15b43..953e7f36467 100644 --- a/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp +++ b/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp @@ -1544,13 +1544,11 @@ Instruction *InstCombiner::visitSRem(BinaryOperator &I) { // If the sign bits of both operands are zero (i.e. we can prove they are // unsigned inputs), turn this into a urem. - if (I.getType()->isIntegerTy()) { - APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits())); - if (MaskedValueIsZero(Op1, Mask, 0, &I) && - MaskedValueIsZero(Op0, Mask, 0, &I)) { - // X srem Y -> X urem Y, iff X and Y don't have sign bit set - return BinaryOperator::CreateURem(Op0, Op1, I.getName()); - } + APInt Mask(APInt::getSignBit(I.getType()->getScalarSizeInBits())); + if (MaskedValueIsZero(Op1, Mask, 0, &I) && + MaskedValueIsZero(Op0, Mask, 0, &I)) { + // X srem Y -> X urem Y, iff X and Y don't have sign bit set + return BinaryOperator::CreateURem(Op0, Op1, I.getName()); } // If it's a constant vector, flip any negative values positive. diff --git a/test/Transforms/InstCombine/rem.ll b/test/Transforms/InstCombine/rem.ll index 00c020fdae8..86a3580189f 100644 --- a/test/Transforms/InstCombine/rem.ll +++ b/test/Transforms/InstCombine/rem.ll @@ -586,7 +586,7 @@ define i32 @test22(i32 %A) { define <2 x i32> @test23(<2 x i32> %A) { ; CHECK-LABEL: @test23( ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[A:%.*]], -; CHECK-NEXT: [[MUL:%.*]] = srem <2 x i32> [[AND]], +; CHECK-NEXT: [[MUL:%.*]] = urem <2 x i32> [[AND]], ; CHECK-NEXT: ret <2 x i32> [[MUL]] ; %and = and <2 x i32> %A,