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https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-24 19:52:54 +01:00
[RISCV] Expand codegen -> compression sanity checks and move to a single file
The objdump tests interfere with update_llc_test_checks.py and can't be automatically update them. Put the sanitify check for compression on the codegen codepath into a separate file, and expand it to also include tests of integer materialisation. This would catch changes such as those triggered by D41949. llvm-svn: 330288
This commit is contained in:
Alex Bradbury
parent
5c52505245
commit
8a1d9129ff
@ -2,10 +2,6 @@
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj < %s \
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; RUN: |llvm-objdump -d -triple=riscv32 -mattr=+c -riscv-no-aliases - \
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; RUN: | FileCheck -check-prefix=RV32IC %s
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; These tests are each targeted at a particular RISC-V ALU instruction. Other
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; files in this folder exercise LLVM IR instructions that don't directly match a
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; RISC-V instruction
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@ -17,10 +13,6 @@ define i32 @addi(i32 %a) nounwind {
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a0, a0, 1
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; RV32I-NEXT: ret
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; RV32IC-LABEL: addi:
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; RV32IC-NEXT: c.addi a0, 1
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; RV32IC-NEXT: c.jr ra
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%1 = add i32 %a, 1
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ret i32 %1
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}
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@ -68,11 +60,6 @@ define i32 @andi(i32 %a) nounwind {
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; RV32I: # %bb.0:
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; RV32I-NEXT: andi a0, a0, 6
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; RV32I-NEXT: ret
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; RV32IC-LABEL: andi:
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; RV32IC: c.andi a0, 6
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; RV32IC: c.jr ra
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%1 = and i32 %a, 6
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ret i32 %1
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}
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@ -82,10 +69,6 @@ define i32 @slli(i32 %a) nounwind {
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 7
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; RV32I-NEXT: ret
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; RV32IC-LABEL: slli:
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; RV32IC-NEXT: slli a0, 7
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; RV32IC-NEXT: c.jr ra
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%1 = shl i32 %a, 7
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ret i32 %1
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}
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@ -95,10 +78,6 @@ define i32 @srli(i32 %a) nounwind {
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; RV32I: # %bb.0:
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; RV32I-NEXT: srli a0, a0, 8
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; RV32I-NEXT: ret
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; RV32IC-LABEL: srli:
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; RV32IC-NEXT: c.srli a0, 8
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; RV32IC-NEXT: c.jr ra
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%1 = lshr i32 %a, 8
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ret i32 %1
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}
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@ -108,10 +87,6 @@ define i32 @srai(i32 %a) nounwind {
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; RV32I: # %bb.0:
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; RV32I-NEXT: srai a0, a0, 9
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; RV32I-NEXT: ret
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; RV32IC-LABEL: srai:
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; RV32IC-NEXT: c.srai a0, 9
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; RV32IC-NEXT: c.jr ra
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%1 = ashr i32 %a, 9
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ret i32 %1
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}
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@ -123,11 +98,6 @@ define i32 @add(i32 %a, i32 %b) nounwind {
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; RV32I: # %bb.0:
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; RV32I-NEXT: add a0, a0, a1
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; RV32I-NEXT: ret
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; RV32IC-LABEL: add:
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; RV32IC-NEXT: c.add a0, a1
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; RV32IC-NEXT: c.jr ra
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%1 = add i32 %a, %b
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ret i32 %1
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}
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@ -137,10 +107,6 @@ define i32 @sub(i32 %a, i32 %b) nounwind {
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; RV32I: # %bb.0:
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; RV32I-NEXT: sub a0, a0, a1
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; RV32I-NEXT: ret
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; RV32IC-LABEL: sub:
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; RV32IC-NEXT: c.sub a0, a1
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; RV32IC-NEXT: c.jr ra
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%1 = sub i32 %a, %b
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ret i32 %1
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}
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@ -179,10 +145,6 @@ define i32 @xor(i32 %a, i32 %b) nounwind {
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; RV32I: # %bb.0:
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: ret
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; RV32IC-LABEL: xor:
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; RV32IC-NEXT: c.xor a0, a1
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; RV32IC-NEXT: c.jr ra
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%1 = xor i32 %a, %b
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ret i32 %1
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}
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@ -219,10 +181,6 @@ define i32 @and(i32 %a, i32 %b) nounwind {
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; RV32I: # %bb.0:
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: ret
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; RV32IC-LABEL: and:
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; RV32IC-NEXT: c.and a0, a1
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; RV32IC-NEXT: c.jr ra
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%1 = and i32 %a, %b
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ret i32 %1
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}
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@ -2,11 +2,6 @@
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj < %s \
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; RUN: |llvm-objdump -d -triple=riscv32 -mattr=+c -riscv-no-aliases - \
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; RUN: | FileCheck -check-prefix=RV32IC %s
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define void @foo(i32 %a, i32 *%b, i1 %c) {
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; RV32I-LABEL: foo:
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; RV32I: # %bb.0:
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@ -47,34 +42,6 @@ define void @foo(i32 %a, i32 *%b, i1 %c) {
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; RV32I-NEXT: lw a0, 0(a1)
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; RV32I-NEXT: .LBB0_12: # %end
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; RV32I-NEXT: ret
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; RV32IC-LABEL: foo:
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; RV32IC: c.lw a3, 0(a1)
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; RV32IC-NEXT: beq a3, a0, 68
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; RV32IC-NEXT: c.lw a3, 0(a1)
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; RV32IC-NEXT: bne a3, a0, 62
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; RV32IC-NEXT: c.lw a3, 0(a1)
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; RV32IC-NEXT: blt a3, a0, 56
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; RV32IC-NEXT: c.lw a3, 0(a1)
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; RV32IC-NEXT: bge a3, a0, 50
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; RV32IC-NEXT: c.lw a3, 0(a1)
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; RV32IC-NEXT: bltu a3, a0, 44
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; RV32IC-NEXT: c.lw a3, 0(a1)
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; RV32IC-NEXT: bgeu a3, a0, 38
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; RV32IC-NEXT: c.lw a3, 0(a1)
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; RV32IC-NEXT: blt a0, a3, 32
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; RV32IC-NEXT: c.lw a3, 0(a1)
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; RV32IC-NEXT: bge a0, a3, 26
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; RV32IC-NEXT: c.lw a3, 0(a1)
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; RV32IC-NEXT: bltu a0, a3, 20
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; RV32IC-NEXT: c.lw a3, 0(a1)
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; RV32IC-NEXT: bgeu a0, a3, 14
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; RV32IC-NEXT: c.lw a0, 0(a1)
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; RV32IC-NEXT: andi a0, a2, 1
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; RV32IC-NEXT: c.bnez a0, 4
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; RV32IC-NEXT: c.lw a0, 0(a1)
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; RV32IC-NEXT: c.jr ra
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%val1 = load volatile i32, i32* %b
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%tst1 = icmp eq i32 %val1, %a
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br i1 %tst1, label %end, label %test2
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@ -1,10 +0,0 @@
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; RUN: llc -mtriple=riscv32 -mattr=+c -riscv-no-aliases -o %t1 < %s
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; RUN: FileCheck %s < %t1
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define void @foo() {
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; CHECK-LABEL: foo:
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; CHECK: c.jr
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end:
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ret void
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}
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169
test/CodeGen/RISCV/compress.ll
Normal file
169
test/CodeGen/RISCV/compress.ll
Normal file
@ -0,0 +1,169 @@
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; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj \
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; RUN: -disable-block-placement < %s \
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; RUN: | llvm-objdump -d -triple=riscv32 -mattr=+c -riscv-no-aliases - \
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; RUN: | FileCheck -check-prefix=RV32IC %s
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; This acts as a sanity check for the codegen instruction compression path,
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; verifying that the assembled file contains compressed instructions when
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; expected. Handling of the compressed ISA is implemented so the same
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; transformation patterns should be used whether compressing an input .s file or
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; compressing codegen output. This file contains sanity checks to ensure that is
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; working as expected. Particular care should be taken to test pseudo
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; instructions.
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; Note: TODOs in this file are only appropriate if they highlight a case where
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; a generated instruction that can be compressed by an existing pattern isn't.
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; It may be useful to have tests that indicate where better compression would be
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; possible if alternative codegen choices were made, but they belong in a
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; different test file.
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define i32 @simple_arith(i32 %a, i32 %b) nounwind {
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; RV32IC-LABEL: simple_arith:
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; RV32IC: c.srai a1, 9
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; RV32IC-NEXT: addi a2, a0, 1
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; RV32IC-NEXT: c.andi a2, 11
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; RV32IC-NEXT: c.slli a2, 7
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; RV32IC-NEXT: c.add a1, a2
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; RV32IC-NEXT: sub a0, a1, a0
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; RV32IC-NEXT: c.jr ra
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%1 = add i32 %a, 1
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%2 = and i32 %1, 11
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%3 = shl i32 %2, 7
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%4 = ashr i32 %b, 9
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%5 = add i32 %3, %4
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%6 = sub i32 %5, %a
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ret i32 %6
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}
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define i32 @select(i32 %a, i32 *%b) nounwind {
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; RV32IC-LABEL: select:
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; RV32IC: c.lw a2, 0(a1)
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; RV32IC-NEXT: c.beqz a2, 4
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a2, 0(a1)
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; RV32IC-NEXT: c.bnez a2, 4
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a2, 0(a1)
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; RV32IC-NEXT: bltu a2, a0, 6
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a2, 0(a1)
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; RV32IC-NEXT: bgeu a0, a2, 6
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a2, 0(a1)
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; RV32IC-NEXT: bltu a0, a2, 6
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a2, 0(a1)
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; RV32IC-NEXT: bgeu a2, a0, 6
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a2, 0(a1)
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; RV32IC-NEXT: blt a2, a0, 6
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a2, 0(a1)
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; RV32IC-NEXT: bge a0, a2, 6
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a2, 0(a1)
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; RV32IC-NEXT: blt a0, a2, 6
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; RV32IC-NEXT: c.mv a0, a2
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; RV32IC-NEXT: c.lw a1, 0(a1)
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; RV32IC-NEXT: bge a1, a0, 6
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; RV32IC-NEXT: c.mv a0, a1
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; RV32IC-NEXT: c.jr ra
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%val1 = load volatile i32, i32* %b
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%tst1 = icmp eq i32 0, %val1
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%val2 = select i1 %tst1, i32 %a, i32 %val1
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%val3 = load volatile i32, i32* %b
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%tst2 = icmp ne i32 0, %val3
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%val4 = select i1 %tst2, i32 %val2, i32 %val3
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%val5 = load volatile i32, i32* %b
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%tst3 = icmp ugt i32 %val4, %val5
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%val6 = select i1 %tst3, i32 %val4, i32 %val5
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%val7 = load volatile i32, i32* %b
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%tst4 = icmp uge i32 %val6, %val7
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%val8 = select i1 %tst4, i32 %val6, i32 %val7
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%val9 = load volatile i32, i32* %b
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%tst5 = icmp ult i32 %val8, %val9
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%val10 = select i1 %tst5, i32 %val8, i32 %val9
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%val11 = load volatile i32, i32* %b
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%tst6 = icmp ule i32 %val10, %val11
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%val12 = select i1 %tst6, i32 %val10, i32 %val11
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%val13 = load volatile i32, i32* %b
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%tst7 = icmp sgt i32 %val12, %val13
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%val14 = select i1 %tst7, i32 %val12, i32 %val13
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%val15 = load volatile i32, i32* %b
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%tst8 = icmp sge i32 %val14, %val15
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%val16 = select i1 %tst8, i32 %val14, i32 %val15
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%val17 = load volatile i32, i32* %b
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%tst9 = icmp slt i32 %val16, %val17
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%val18 = select i1 %tst9, i32 %val16, i32 %val17
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%val19 = load volatile i32, i32* %b
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%tst10 = icmp sle i32 %val18, %val19
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%val20 = select i1 %tst10, i32 %val18, i32 %val19
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ret i32 %val20
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}
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define i32 @pos_tiny() nounwind {
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; RV32IC-LABEL: pos_tiny:
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; RV32IC: c.li a0, 18
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; RV32IC-NEXT: c.jr ra
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ret i32 18
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}
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define i32 @pos_i32() nounwind {
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; RV32IC-LABEL: pos_i32:
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; RV32IC: lui a0, 423811
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; RV32IC-NEXT: addi a0, a0, -1297
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; RV32IC-NEXT: c.jr ra
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ret i32 1735928559
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}
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define i32 @pos_i32_half_compressible() nounwind {
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; RV32IC-LABEL: pos_i32_half_compressible:
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; RV32IC: lui a0, 423810
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; RV32IC-NEXT: c.addi a0, 28
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; RV32IC-NEXT: c.jr ra
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ret i32 1735925788
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}
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define i32 @neg_tiny() nounwind {
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; RV32IC-LABEL: neg_tiny:
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; RV32IC: c.li a0, -19
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; RV32IC-NEXT: c.jr ra
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ret i32 -19
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}
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define i32 @neg_i32() nounwind {
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; RV32IC-LABEL: neg_i32:
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; RV32IC: lui a0, 912092
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; RV32IC-NEXT: addi a0, a0, -273
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; RV32IC-NEXT: c.jr ra
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ret i32 -559038737
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}
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; TODO: c.mv is unnecessary.
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define i32 @pos_i32_hi20_only() nounwind {
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; RV32IC-LABEL: pos_i32_hi20_only:
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; RV32IC: c.lui a0, 16
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; RV32IC: c.mv a0, a0
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; RV32IC-NEXT: c.jr ra
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ret i32 65536
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}
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; TODO: c.mv is unnecessary.
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define i32 @neg_i32_hi20_only() nounwind {
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; RV32IC-LABEL: neg_i32_hi20_only:
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; RV32IC: c.lui a0, 1048560
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; RV32IC: c.mv a0, a0
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; RV32IC-NEXT: c.jr ra
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ret i32 -65536
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}
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