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[mips] Modify definitions of floating point conditional move instructions.
No functionality change. llvm-svn: 170080
This commit is contained in:
Akira Hatanaka
parent
a1d639a0ea
commit
8a20e0e5f7
@ -56,6 +56,31 @@ class CondMovFPFP<RegisterClass RC, SDNode cmov, bits<5> fmt, bits<1> tf,
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let Constraints = "$F = $fd";
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}
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class CMov_I_F_FT<string opstr, RegisterClass CRC, RegisterClass DRC,
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InstrItinClass Itin> :
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InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
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!strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR> {
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let Constraints = "$F = $fd";
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}
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class CMov_F_I_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
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SDPatternOperator OpNode = null_frag> :
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InstSE<(outs RC:$rd), (ins RC:$rs, RC:$F),
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!strconcat(opstr, "\t$rd, $rs, $$fcc0"),
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[(set RC:$rd, (OpNode RC:$rs, RC:$F))], Itin, FrmFR> {
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let Uses = [FCR31];
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let Constraints = "$F = $rd";
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}
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class CMov_F_F_FT<string opstr, RegisterClass RC, InstrItinClass Itin,
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SDPatternOperator OpNode = null_frag> :
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InstSE<(outs RC:$fd), (ins RC:$fs, RC:$F),
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!strconcat(opstr, "\t$fd, $fs, $$fcc0"),
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[(set RC:$fd, (OpNode RC:$fs, RC:$F))], Itin, FrmFR> {
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let Uses = [FCR31];
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let Constraints = "$F = $fd";
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}
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// select patterns
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multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
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Instruction MOVZInst, Instruction SLTOp,
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@ -130,57 +155,71 @@ let Predicates = [HasStdEnc],
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}
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}
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def MOVZ_I_S : CondMovIntFP<CPURegs, FGR32, 16, 18, "movz.s">;
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def MOVZ_I64_S : CondMovIntFP<CPU64Regs, FGR32, 16, 18, "movz.s">,
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Requires<[HasMips64, HasStdEnc]> {
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def MOVZ_I_S : CMov_I_F_FT<"movz.s", CPURegs, FGR32, IIFmove>,
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CMov_I_F_FM<18, 16>;
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def MOVZ_I64_S : CMov_I_F_FT<"movz.s", CPU64Regs, FGR32, IIFmove>,
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CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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}
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def MOVN_I_S : CondMovIntFP<CPURegs, FGR32, 16, 19, "movn.s">;
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def MOVN_I64_S : CondMovIntFP<CPU64Regs, FGR32, 16, 19, "movn.s">,
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Requires<[HasMips64, HasStdEnc]> {
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def MOVN_I_S : CMov_I_F_FT<"movn.s", CPURegs, FGR32, IIFmove>,
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CMov_I_F_FM<19, 16>;
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def MOVN_I64_S : CMov_I_F_FT<"movn.s", CPU64Regs, FGR32, IIFmove>,
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CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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}
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let Predicates = [NotFP64bit, HasStdEnc] in {
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def MOVZ_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 18, "movz.d">;
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def MOVN_I_D32 : CondMovIntFP<CPURegs, AFGR64, 17, 19, "movn.d">;
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def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", CPURegs, AFGR64, IIFmove>,
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CMov_I_F_FM<18, 17>;
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def MOVN_I_D32 : CMov_I_F_FT<"movn.d", CPURegs, AFGR64, IIFmove>,
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CMov_I_F_FM<19, 17>;
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}
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let Predicates = [IsFP64bit, HasStdEnc],
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DecoderNamespace = "Mips64" in {
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def MOVZ_I_D64 : CondMovIntFP<CPURegs, FGR64, 17, 18, "movz.d">;
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def MOVZ_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 18, "movz.d"> {
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def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", CPURegs, FGR64, IIFmove>,
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CMov_I_F_FM<18, 17>;
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def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", CPU64Regs, FGR64, IIFmove>,
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CMov_I_F_FM<18, 17> {
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let isCodeGenOnly = 1;
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}
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def MOVN_I_D64 : CondMovIntFP<CPURegs, FGR64, 17, 19, "movn.d">;
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def MOVN_I64_D64 : CondMovIntFP<CPU64Regs, FGR64, 17, 19, "movn.d"> {
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def MOVN_I_D64 : CMov_I_F_FT<"movn.d", CPURegs, FGR64, IIFmove>,
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CMov_I_F_FM<19, 17>;
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def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", CPU64Regs, FGR64, IIFmove>,
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CMov_I_F_FM<19, 17> {
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let isCodeGenOnly = 1;
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}
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}
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def MOVT_I : CondMovFPInt<CPURegs, MipsCMovFP_T, 1, "movt">;
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def MOVT_I64 : CondMovFPInt<CPU64Regs, MipsCMovFP_T, 1, "movt">,
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Requires<[HasMips64, HasStdEnc]> {
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def MOVT_I : CMov_F_I_FT<"movt", CPURegs, IIAlu, MipsCMovFP_T>, CMov_F_I_FM<1>;
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def MOVT_I64 : CMov_F_I_FT<"movt", CPU64Regs, IIAlu, MipsCMovFP_T>,
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CMov_F_I_FM<1>, Requires<[HasMips64, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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}
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def MOVF_I : CondMovFPInt<CPURegs, MipsCMovFP_F, 0, "movf">;
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def MOVF_I64 : CondMovFPInt<CPU64Regs, MipsCMovFP_F, 0, "movf">,
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Requires<[HasMips64, HasStdEnc]> {
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def MOVF_I : CMov_F_I_FT<"movf", CPURegs, IIAlu, MipsCMovFP_F>, CMov_F_I_FM<0>;
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def MOVF_I64 : CMov_F_I_FT<"movf", CPU64Regs, IIAlu, MipsCMovFP_F>,
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CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]> {
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let DecoderNamespace = "Mips64";
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}
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def MOVT_S : CondMovFPFP<FGR32, MipsCMovFP_T, 16, 1, "movt.s">;
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def MOVF_S : CondMovFPFP<FGR32, MipsCMovFP_F, 16, 0, "movf.s">;
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def MOVT_S : CMov_F_F_FT<"movt.s", FGR32, IIFmove, MipsCMovFP_T>,
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CMov_F_F_FM<16, 1>;
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def MOVF_S : CMov_F_F_FT<"movf.s", FGR32, IIFmove, MipsCMovFP_F>,
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CMov_F_F_FM<16, 0>;
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let Predicates = [NotFP64bit, HasStdEnc] in {
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def MOVT_D32 : CondMovFPFP<AFGR64, MipsCMovFP_T, 17, 1, "movt.d">;
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def MOVF_D32 : CondMovFPFP<AFGR64, MipsCMovFP_F, 17, 0, "movf.d">;
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def MOVT_D32 : CMov_F_F_FT<"movt.d", AFGR64, IIFmove, MipsCMovFP_T>,
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CMov_F_F_FM<17, 1>;
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def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64, IIFmove, MipsCMovFP_F>,
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CMov_F_F_FM<17, 0>;
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}
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let Predicates = [IsFP64bit, HasStdEnc],
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DecoderNamespace = "Mips64" in {
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def MOVT_D64 : CondMovFPFP<FGR64, MipsCMovFP_T, 17, 1, "movt.d">;
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def MOVF_D64 : CondMovFPFP<FGR64, MipsCMovFP_F, 17, 0, "movf.d">;
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def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64, IIFmove, MipsCMovFP_T>,
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CMov_F_F_FM<17, 1>;
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def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64, IIFmove, MipsCMovFP_F>,
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CMov_F_F_FM<17, 0>;
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}
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// Instantiation of conditional move patterns.
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@ -482,3 +482,50 @@ class CEQS_FM<bits<5> fmt> {
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let Inst{7-4} = 0x3;
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let Inst{3-0} = cond;
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}
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class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
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bits<5> fd;
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bits<5> fs;
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bits<5> rt;
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bits<32> Inst;
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let Inst{31-26} = 0x11;
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let Inst{25-21} = fmt;
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let Inst{20-16} = rt;
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5-0} = funct;
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}
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class CMov_F_I_FM<bit tf> {
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bits<5> rd;
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bits<5> rs;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = rs;
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let Inst{20-18} = 0; // cc
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let Inst{17} = 0;
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let Inst{16} = tf;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0;
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let Inst{5-0} = 1;
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}
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class CMov_F_F_FM<bits<5> fmt, bit tf> {
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bits<5> fd;
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bits<5> fs;
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bits<32> Inst;
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let Inst{31-26} = 0x11;
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let Inst{25-21} = fmt;
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let Inst{20-18} = 0; // cc
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let Inst{17} = 0;
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let Inst{16} = tf;
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let Inst{15-11} = fs;
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let Inst{10-6} = fd;
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let Inst{5-0} = 0x11;
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}
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