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[DAGCombiner] Set the right SDLoc on a newly-created sextload (6/N)
This teaches tryToFoldExtOfLoad to set the right location on a newly-created extload. With that in place, the logic for performing a certain ([s|z]ext (load ...)) combine becomes identical for sexts and zexts, and we can get rid of one copy of the logic. The test case churn is due to dependencies on IROrders inherited from the wrong SDLoc. Part of: llvm.org/PR37262 Differential Revision: https://reviews.llvm.org/D46158 llvm-svn: 332118
This commit is contained in:
Vedant Kumar
parent
95b78428ff
commit
8a31d7c70d
@ -7782,9 +7782,9 @@ static SDValue tryToFoldExtOfLoad(SelectionDAG &DAG, DAGCombiner &Combiner,
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return {};
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LoadSDNode *LN0 = cast<LoadSDNode>(N0);
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SDValue ExtLoad =
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DAG.getExtLoad(ExtLoadType, DL, VT, LN0->getChain(), LN0->getBasePtr(),
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N0.getValueType(), LN0->getMemOperand());
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SDValue ExtLoad = DAG.getExtLoad(ExtLoadType, SDLoc(LN0), VT, LN0->getChain(),
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LN0->getBasePtr(), N0.getValueType(),
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LN0->getMemOperand());
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Combiner.ExtendSetCCUses(SetCCs, N0, ExtLoad, DL, ExtOpc);
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// If the load value is used only by N, replace it via CombineTo N.
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bool NoReplaceTrunc = SDValue(LN0, 0).hasOneUse();
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@ -8131,41 +8131,11 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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X, DAG.getConstant(Mask, DL, VT));
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}
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// fold (zext (load x)) -> (zext (truncate (zextload x)))
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// Only generate vector extloads when 1) they're legal, and 2) they are
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// deemed desirable by the target.
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if (ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
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((!LegalOperations && !VT.isVector() &&
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!cast<LoadSDNode>(N0)->isVolatile()) ||
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TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()))) {
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bool DoXform = true;
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SmallVector<SDNode*, 4> SetCCs;
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if (!N0.hasOneUse())
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DoXform = ExtendUsesToFormExtLoad(VT, N, N0, ISD::ZERO_EXTEND, SetCCs,
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TLI);
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if (VT.isVector())
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DoXform &= TLI.isVectorLoadExtDesirable(SDValue(N, 0));
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if (DoXform) {
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LoadSDNode *LN0 = cast<LoadSDNode>(N0);
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SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), VT,
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LN0->getChain(),
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LN0->getBasePtr(), N0.getValueType(),
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LN0->getMemOperand());
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ExtendSetCCUses(SetCCs, N0, ExtLoad, SDLoc(N), ISD::ZERO_EXTEND);
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// If the load value is used only by N, replace it via CombineTo N.
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bool NoReplaceTrunc = SDValue(LN0, 0).hasOneUse();
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CombineTo(N, ExtLoad);
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if (NoReplaceTrunc) {
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DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), ExtLoad.getValue(1));
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} else {
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SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
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N0.getValueType(), ExtLoad);
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CombineTo(LN0, Trunc, ExtLoad.getValue(1));
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}
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return SDValue(N, 0); // Return N so it doesn't get rechecked!
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}
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}
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// Try to simplify (zext (load x)).
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if (SDValue foldedExt =
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tryToFoldExtOfLoad(DAG, *this, TLI, VT, LegalOperations, N, N0,
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SDLoc(N), ISD::ZEXTLOAD, ISD::ZERO_EXTEND))
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return foldedExt;
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// fold (zext (load x)) to multiple smaller zextloads.
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// Only on illegal but splittable vectors.
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@ -67,14 +67,14 @@ define i32 @ldur_int(i32* %a) nounwind {
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; Test sext + zext clustering.
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; CHECK: ********** MI Scheduling **********
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; CHECK-LABEL: ldp_half_sext_zext_int:%bb.0
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; CHECK: Cluster ld/st SU(4) - SU(3)
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; CHECK: SU(3): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
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; CHECK: SU(4): %{{[0-9]+}}:gpr64 = LDRSWui
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; CHECK: Cluster ld/st SU(3) - SU(4)
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; CHECK: SU(3): %{{[0-9]+}}:gpr64 = LDRSWui
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; CHECK: SU(4): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
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; EXYNOSM1: ********** MI Scheduling **********
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; EXYNOSM1-LABEL: ldp_half_sext_zext_int:%bb.0
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; EXYNOSM1: Cluster ld/st SU(4) - SU(3)
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; EXYNOSM1: SU(3): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
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; EXYNOSM1: SU(4): %{{[0-9]+}}:gpr64 = LDRSWui
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; EXYNOSM1: Cluster ld/st SU(3) - SU(4)
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; EXYNOSM1: SU(3): %{{[0-9]+}}:gpr64 = LDRSWui
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; EXYNOSM1: SU(4): undef %{{[0-9]+}}.sub_32:gpr64 = LDRWui
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define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind {
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%tmp0 = load i64, i64* %q, align 4
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%tmp = load i32, i32* %p, align 4
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@ -1949,6 +1949,8 @@ define i96 @test_insertelement_variable_v96i1(<96 x i8> %a, i8 %b, i32 %index) {
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; KNL-NEXT: vpinsrb $14, 208(%rbp), %xmm3, %xmm3
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; KNL-NEXT: vpinsrb $15, 216(%rbp), %xmm3, %xmm3
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; KNL-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
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; KNL-NEXT: movl 744(%rbp), %eax
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; KNL-NEXT: andl $127, %eax
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; KNL-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; KNL-NEXT: vpcmpeqb %ymm3, %ymm2, %ymm2
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; KNL-NEXT: vpternlogq $15, %zmm2, %zmm2, %zmm2
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@ -1956,8 +1958,6 @@ define i96 @test_insertelement_variable_v96i1(<96 x i8> %a, i8 %b, i32 %index) {
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; KNL-NEXT: vpternlogq $15, %zmm1, %zmm1, %zmm1
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; KNL-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm0
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; KNL-NEXT: vpternlogq $15, %zmm0, %zmm0, %zmm0
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; KNL-NEXT: movl 744(%rbp), %eax
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; KNL-NEXT: andl $127, %eax
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; KNL-NEXT: cmpb $0, 736(%rbp)
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; KNL-NEXT: vmovdqa %ymm3, {{[0-9]+}}(%rsp)
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; KNL-NEXT: vmovdqa %ymm0, {{[0-9]+}}(%rsp)
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@ -2130,10 +2130,10 @@ define i96 @test_insertelement_variable_v96i1(<96 x i8> %a, i8 %b, i32 %index) {
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; SKX-NEXT: vpinsrb $14, 720(%rbp), %xmm2, %xmm2
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; SKX-NEXT: vpinsrb $15, 728(%rbp), %xmm2, %xmm2
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; SKX-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
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; SKX-NEXT: vptestmb %zmm0, %zmm0, %k0
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; SKX-NEXT: vptestmb %zmm1, %zmm1, %k1
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; SKX-NEXT: movl 744(%rbp), %eax
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; SKX-NEXT: andl $127, %eax
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; SKX-NEXT: vptestmb %zmm0, %zmm0, %k0
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; SKX-NEXT: vptestmb %zmm1, %zmm1, %k1
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; SKX-NEXT: cmpb $0, 736(%rbp)
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; SKX-NEXT: vpmovm2b %k1, %zmm0
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; SKX-NEXT: vmovdqa64 %zmm0, {{[0-9]+}}(%rsp)
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@ -1,20 +1,61 @@
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; RUN: llc < %s -mtriple=x86_64-- | grep movslq | count 1
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; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -stop-after livedebugvalues -o - | FileCheck %s -check-prefix=MIR
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; PR4050
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%0 = type { i64 } ; type %0
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%struct.S1 = type { i16, i32 }
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@g_10 = external global %struct.S1 ; <%struct.S1*> [#uses=2]
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%0 = type { i64 }
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%struct.S1 = type { i16, i32 }
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@g_10 = external global %struct.S1
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declare void @func_28(i64, i64)
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define void @int322(i32 %foo) nounwind {
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define void @int322(i32 %foo) !dbg !5 {
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entry:
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%val = load i64, i64* getelementptr (%0, %0* bitcast (%struct.S1* @g_10 to %0*), i32 0, i32 0) ; <i64> [#uses=1]
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%0 = load i32, i32* getelementptr (%struct.S1, %struct.S1* @g_10, i32 0, i32 1), align 4 ; <i32> [#uses=1]
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%1 = sext i32 %0 to i64 ; <i64> [#uses=1]
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%tmp4.i = lshr i64 %val, 32 ; <i64> [#uses=1]
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%tmp5.i = trunc i64 %tmp4.i to i32 ; <i32> [#uses=1]
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%2 = sext i32 %tmp5.i to i64 ; <i64> [#uses=1]
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tail call void @func_28(i64 %2, i64 %1) nounwind
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ret void
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%val = load i64, i64* getelementptr (%0, %0* bitcast (%struct.S1* @g_10 to %0*), i32 0, i32 0), !dbg !16
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%0 = load i32, i32* getelementptr inbounds (%struct.S1, %struct.S1* @g_10, i32 0, i32 1), align 4, !dbg !17
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; MIR: renamable $rax = MOVSX64rm32 {{.*}}, @g_10 + 4,{{.*}} debug-location !17 :: (dereferenceable load 4 from `i64* getelementptr (%0, %0* bitcast (%struct.S1* @g_10 to %0*), i32 0, i32 0)` + 4)
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%1 = sext i32 %0 to i64, !dbg !18
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%tmp4.i = lshr i64 %val, 32, !dbg !19
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%tmp5.i = trunc i64 %tmp4.i to i32, !dbg !20
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%2 = sext i32 %tmp5.i to i64, !dbg !21
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tail call void @func_28(i64 %2, i64 %1) #0, !dbg !22
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call void @llvm.dbg.value(metadata i64 %val, metadata !8, metadata !DIExpression()), !dbg !16
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call void @llvm.dbg.value(metadata i32 %0, metadata !10, metadata !DIExpression()), !dbg !17
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call void @llvm.dbg.value(metadata i64 %1, metadata !12, metadata !DIExpression()), !dbg !18
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call void @llvm.dbg.value(metadata i64 %tmp4.i, metadata !13, metadata !DIExpression()), !dbg !19
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call void @llvm.dbg.value(metadata i32 %tmp5.i, metadata !14, metadata !DIExpression()), !dbg !20
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call void @llvm.dbg.value(metadata i64 %2, metadata !15, metadata !DIExpression()), !dbg !21
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ret void, !dbg !23
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}
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declare void @llvm.dbg.value(metadata, metadata, metadata)
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!llvm.dbg.cu = !{!0}
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!llvm.debugify = !{!3, !4}
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!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
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!1 = !DIFile(filename: "/Users/vsk/src/llvm.org-master/llvm/test/CodeGen/X86/fold-sext-trunc.ll", directory: "/")
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!2 = !{}
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!3 = !{i32 8}
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!4 = !{i32 6}
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!5 = distinct !DISubprogram(name: "int322", linkageName: "int322", scope: null, file: !1, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 1, isOptimized: true, unit: !0, retainedNodes: !7)
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!6 = !DISubroutineType(types: !2)
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!7 = !{!8, !10, !12, !13, !14, !15}
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!8 = !DILocalVariable(name: "1", scope: !5, file: !1, line: 1, type: !9)
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!9 = !DIBasicType(name: "ty64", size: 64, encoding: DW_ATE_unsigned)
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!10 = !DILocalVariable(name: "2", scope: !5, file: !1, line: 2, type: !11)
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!11 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_unsigned)
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!12 = !DILocalVariable(name: "3", scope: !5, file: !1, line: 3, type: !9)
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!13 = !DILocalVariable(name: "4", scope: !5, file: !1, line: 4, type: !9)
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!14 = !DILocalVariable(name: "5", scope: !5, file: !1, line: 5, type: !11)
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!15 = !DILocalVariable(name: "6", scope: !5, file: !1, line: 6, type: !9)
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!16 = !DILocation(line: 1, column: 1, scope: !5)
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!17 = !DILocation(line: 2, column: 1, scope: !5)
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!18 = !DILocation(line: 3, column: 1, scope: !5)
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!19 = !DILocation(line: 4, column: 1, scope: !5)
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!20 = !DILocation(line: 5, column: 1, scope: !5)
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!21 = !DILocation(line: 6, column: 1, scope: !5)
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!22 = !DILocation(line: 7, column: 1, scope: !5)
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!23 = !DILocation(line: 8, column: 1, scope: !5)
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!24 = !{i32 2, !"Debug Info Version", i32 3}
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!llvm.module.flags = !{!24}
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@ -25,10 +25,10 @@ define <2 x double> @signbits_sext_v2i64_sitofp_v2f64(i32 %a0, i32 %a1) nounwind
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define <4 x float> @signbits_sext_v4i64_sitofp_v4f32(i8 signext %a0, i16 signext %a1, i32 %a2, i32 %a3) nounwind {
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; X32-LABEL: signbits_sext_v4i64_sitofp_v4f32:
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; X32: # %bb.0:
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; X32-NEXT: movsbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movswl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: vmovd %eax, %xmm0
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; X32-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
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; X32-NEXT: movswl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movsbl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: vmovd %ecx, %xmm0
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; X32-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
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; X32-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X32-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm1, %xmm1
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; X32-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
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@ -270,6 +270,7 @@ define float @signbits_ashr_sext_sextinreg_and_extract_sitofp(<2 x i64> %a0, <2
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; X32-LABEL: signbits_ashr_sext_sextinreg_and_extract_sitofp:
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; X32: # %bb.0:
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; X32-NEXT: pushl %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: vmovdqa {{.*#+}} xmm2 = [0,2147483648,0,2147483648]
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; X32-NEXT: vpsrlq $60, %xmm2, %xmm3
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; X32-NEXT: vpsrlq $61, %xmm2, %xmm2
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@ -279,7 +280,6 @@ define float @signbits_ashr_sext_sextinreg_and_extract_sitofp(<2 x i64> %a0, <2
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; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
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; X32-NEXT: vpxor %xmm2, %xmm0, %xmm0
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; X32-NEXT: vpsubq %xmm2, %xmm0, %xmm0
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: vpinsrd $0, %eax, %xmm1, %xmm1
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; X32-NEXT: sarl $31, %eax
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; X32-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
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@ -202,31 +202,31 @@ define void @f1() {
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; 686-O0-NEXT: setne {{[0-9]+}}(%esp)
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; 686-O0-NEXT: movl var_5, %ecx
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; 686-O0-NEXT: movl %ecx, %edx
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; 686-O0-NEXT: subl $-1, %edx
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; 686-O0-NEXT: sarl $31, %edx
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; 686-O0-NEXT: movl %ecx, %esi
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; 686-O0-NEXT: subl $-1, %esi
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; 686-O0-NEXT: sete %bl
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; 686-O0-NEXT: movzbl %bl, %esi
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; 686-O0-NEXT: movl %ecx, %edi
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; 686-O0-NEXT: sarl $31, %edi
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; 686-O0-NEXT: movzbl %bl, %edi
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; 686-O0-NEXT: xorl %ebp, %ebp
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; 686-O0-NEXT: addl $7093, %ecx # imm = 0x1BB5
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; 686-O0-NEXT: adcxl %ebp, %edi
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; 686-O0-NEXT: subl %esi, %ecx
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; 686-O0-NEXT: sbbl $0, %edi
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; 686-O0-NEXT: adcxl %ebp, %edx
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; 686-O0-NEXT: subl %edi, %ecx
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; 686-O0-NEXT: sbbl $0, %edx
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; 686-O0-NEXT: setl %bl
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; 686-O0-NEXT: movzbl %bl, %esi
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; 686-O0-NEXT: movl %esi, var_57
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; 686-O0-NEXT: movzbl %bl, %edi
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; 686-O0-NEXT: movl %edi, var_57
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; 686-O0-NEXT: movl $0, var_57+4
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; 686-O0-NEXT: movl var_5, %esi
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; 686-O0-NEXT: subl $-1, %esi
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; 686-O0-NEXT: movl var_5, %edi
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; 686-O0-NEXT: subl $-1, %edi
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; 686-O0-NEXT: sete %bl
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; 686-O0-NEXT: movzbl %bl, %ebp
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; 686-O0-NEXT: movl %ebp, _ZN8struct_210member_2_0E
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; 686-O0-NEXT: movl $0, _ZN8struct_210member_2_0E+4
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; 686-O0-NEXT: movl %eax, {{[0-9]+}}(%esp) # 4-byte Spill
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; 686-O0-NEXT: movl %ecx, {{[0-9]+}}(%esp) # 4-byte Spill
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; 686-O0-NEXT: movl %edx, {{[0-9]+}}(%esp) # 4-byte Spill
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; 686-O0-NEXT: movl %edi, {{[0-9]+}}(%esp) # 4-byte Spill
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; 686-O0-NEXT: movl %esi, (%esp) # 4-byte Spill
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; 686-O0-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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; 686-O0-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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; 686-O0-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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; 686-O0-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
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; 686-O0-NEXT: movl %edi, (%esp) # 4-byte Spill
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; 686-O0-NEXT: addl $24, %esp
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; 686-O0-NEXT: .cfi_def_cfa_offset 20
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; 686-O0-NEXT: popl %esi
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|
||||
@ -244,6 +244,10 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xxxxxxxx_i16(<8 x i16> %x, i16 %i0, i1
|
||||
; SSE2-NEXT: # kill: def $edx killed $edx def $rdx
|
||||
; SSE2-NEXT: # kill: def $esi killed $esi def $rsi
|
||||
; SSE2-NEXT: # kill: def $edi killed $edi def $rdi
|
||||
; SSE2-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d
|
||||
; SSE2-NEXT: andl $7, %r10d
|
||||
; SSE2-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
|
||||
; SSE2-NEXT: andl $7, %eax
|
||||
; SSE2-NEXT: andl $7, %edi
|
||||
; SSE2-NEXT: andl $7, %esi
|
||||
; SSE2-NEXT: andl $7, %edx
|
||||
@ -251,10 +255,6 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xxxxxxxx_i16(<8 x i16> %x, i16 %i0, i1
|
||||
; SSE2-NEXT: andl $7, %r8d
|
||||
; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSE2-NEXT: andl $7, %r9d
|
||||
; SSE2-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d
|
||||
; SSE2-NEXT: andl $7, %r10d
|
||||
; SSE2-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
|
||||
; SSE2-NEXT: andl $7, %eax
|
||||
; SSE2-NEXT: movzwl -24(%rsp,%rcx,2), %ecx
|
||||
; SSE2-NEXT: movd %ecx, %xmm0
|
||||
; SSE2-NEXT: movzwl -24(%rsp,%rdx,2), %ecx
|
||||
@ -288,6 +288,10 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xxxxxxxx_i16(<8 x i16> %x, i16 %i0, i1
|
||||
; SSSE3-NEXT: # kill: def $edx killed $edx def $rdx
|
||||
; SSSE3-NEXT: # kill: def $esi killed $esi def $rsi
|
||||
; SSSE3-NEXT: # kill: def $edi killed $edi def $rdi
|
||||
; SSSE3-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d
|
||||
; SSSE3-NEXT: andl $7, %r10d
|
||||
; SSSE3-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
|
||||
; SSSE3-NEXT: andl $7, %eax
|
||||
; SSSE3-NEXT: andl $7, %edi
|
||||
; SSSE3-NEXT: andl $7, %esi
|
||||
; SSSE3-NEXT: andl $7, %edx
|
||||
@ -295,10 +299,6 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xxxxxxxx_i16(<8 x i16> %x, i16 %i0, i1
|
||||
; SSSE3-NEXT: andl $7, %r8d
|
||||
; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSSE3-NEXT: andl $7, %r9d
|
||||
; SSSE3-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d
|
||||
; SSSE3-NEXT: andl $7, %r10d
|
||||
; SSSE3-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
|
||||
; SSSE3-NEXT: andl $7, %eax
|
||||
; SSSE3-NEXT: movzwl -24(%rsp,%rcx,2), %ecx
|
||||
; SSSE3-NEXT: movd %ecx, %xmm0
|
||||
; SSSE3-NEXT: movzwl -24(%rsp,%rdx,2), %ecx
|
||||
@ -332,6 +332,10 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xxxxxxxx_i16(<8 x i16> %x, i16 %i0, i1
|
||||
; SSE41-NEXT: # kill: def $edx killed $edx def $rdx
|
||||
; SSE41-NEXT: # kill: def $esi killed $esi def $rsi
|
||||
; SSE41-NEXT: # kill: def $edi killed $edi def $rdi
|
||||
; SSE41-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d
|
||||
; SSE41-NEXT: andl $7, %r10d
|
||||
; SSE41-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
|
||||
; SSE41-NEXT: andl $7, %eax
|
||||
; SSE41-NEXT: andl $7, %edi
|
||||
; SSE41-NEXT: andl $7, %esi
|
||||
; SSE41-NEXT: andl $7, %edx
|
||||
@ -339,10 +343,6 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xxxxxxxx_i16(<8 x i16> %x, i16 %i0, i1
|
||||
; SSE41-NEXT: andl $7, %r8d
|
||||
; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSE41-NEXT: andl $7, %r9d
|
||||
; SSE41-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d
|
||||
; SSE41-NEXT: andl $7, %r10d
|
||||
; SSE41-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
|
||||
; SSE41-NEXT: andl $7, %eax
|
||||
; SSE41-NEXT: movzwl -24(%rsp,%rdi,2), %edi
|
||||
; SSE41-NEXT: movd %edi, %xmm0
|
||||
; SSE41-NEXT: pinsrw $1, -24(%rsp,%rsi,2), %xmm0
|
||||
@ -350,8 +350,8 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xxxxxxxx_i16(<8 x i16> %x, i16 %i0, i1
|
||||
; SSE41-NEXT: pinsrw $3, -24(%rsp,%rcx,2), %xmm0
|
||||
; SSE41-NEXT: pinsrw $4, -24(%rsp,%r8,2), %xmm0
|
||||
; SSE41-NEXT: pinsrw $5, -24(%rsp,%r9,2), %xmm0
|
||||
; SSE41-NEXT: pinsrw $6, -24(%rsp,%r10,2), %xmm0
|
||||
; SSE41-NEXT: pinsrw $7, -24(%rsp,%rax,2), %xmm0
|
||||
; SSE41-NEXT: pinsrw $6, -24(%rsp,%rax,2), %xmm0
|
||||
; SSE41-NEXT: pinsrw $7, -24(%rsp,%r10,2), %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: var_shuffle_v8i16_v8i16_xxxxxxxx_i16:
|
||||
@ -362,6 +362,10 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xxxxxxxx_i16(<8 x i16> %x, i16 %i0, i1
|
||||
; AVX-NEXT: # kill: def $edx killed $edx def $rdx
|
||||
; AVX-NEXT: # kill: def $esi killed $esi def $rsi
|
||||
; AVX-NEXT: # kill: def $edi killed $edi def $rdi
|
||||
; AVX-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d
|
||||
; AVX-NEXT: andl $7, %r10d
|
||||
; AVX-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
|
||||
; AVX-NEXT: andl $7, %eax
|
||||
; AVX-NEXT: andl $7, %edi
|
||||
; AVX-NEXT: andl $7, %esi
|
||||
; AVX-NEXT: andl $7, %edx
|
||||
@ -369,10 +373,6 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xxxxxxxx_i16(<8 x i16> %x, i16 %i0, i1
|
||||
; AVX-NEXT: andl $7, %r8d
|
||||
; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; AVX-NEXT: andl $7, %r9d
|
||||
; AVX-NEXT: movzwl {{[0-9]+}}(%rsp), %r10d
|
||||
; AVX-NEXT: andl $7, %r10d
|
||||
; AVX-NEXT: movzwl {{[0-9]+}}(%rsp), %eax
|
||||
; AVX-NEXT: andl $7, %eax
|
||||
; AVX-NEXT: movzwl -24(%rsp,%rdi,2), %edi
|
||||
; AVX-NEXT: vmovd %edi, %xmm0
|
||||
; AVX-NEXT: vpinsrw $1, -24(%rsp,%rsi,2), %xmm0, %xmm0
|
||||
@ -380,8 +380,8 @@ define <8 x i16> @var_shuffle_v8i16_v8i16_xxxxxxxx_i16(<8 x i16> %x, i16 %i0, i1
|
||||
; AVX-NEXT: vpinsrw $3, -24(%rsp,%rcx,2), %xmm0, %xmm0
|
||||
; AVX-NEXT: vpinsrw $4, -24(%rsp,%r8,2), %xmm0, %xmm0
|
||||
; AVX-NEXT: vpinsrw $5, -24(%rsp,%r9,2), %xmm0, %xmm0
|
||||
; AVX-NEXT: vpinsrw $6, -24(%rsp,%r10,2), %xmm0, %xmm0
|
||||
; AVX-NEXT: vpinsrw $7, -24(%rsp,%rax,2), %xmm0, %xmm0
|
||||
; AVX-NEXT: vpinsrw $6, -24(%rsp,%rax,2), %xmm0, %xmm0
|
||||
; AVX-NEXT: vpinsrw $7, -24(%rsp,%r10,2), %xmm0, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
%x0 = extractelement <8 x i16> %x, i16 %i0
|
||||
%x1 = extractelement <8 x i16> %x, i16 %i1
|
||||
@ -411,9 +411,9 @@ define <16 x i8> @var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8(<16 x i8> %x, i8 %
|
||||
; SSE2-NEXT: # kill: def $edx killed $edx def $rdx
|
||||
; SSE2-NEXT: # kill: def $esi killed $esi def $rsi
|
||||
; SSE2-NEXT: # kill: def $edi killed $edi def $rdi
|
||||
; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
|
||||
; SSE2-NEXT: andl $15, %eax
|
||||
; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rax), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm8
|
||||
; SSE2-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
|
||||
@ -495,9 +495,9 @@ define <16 x i8> @var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8(<16 x i8> %x, i8 %
|
||||
; SSSE3-NEXT: # kill: def $edx killed $edx def $rdx
|
||||
; SSSE3-NEXT: # kill: def $esi killed $esi def $rsi
|
||||
; SSSE3-NEXT: # kill: def $edi killed $edi def $rdi
|
||||
; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
|
||||
; SSSE3-NEXT: andl $15, %eax
|
||||
; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rax), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm8
|
||||
; SSSE3-NEXT: movzbl {{[0-9]+}}(%rsp), %eax
|
||||
@ -723,12 +723,12 @@ define <4 x i32> @mem_shuffle_v4i32_v4i32_xxxx_i32(<4 x i32> %x, i32* %i) nounwi
|
||||
; SSE2-NEXT: movl (%rdi), %eax
|
||||
; SSE2-NEXT: movl 4(%rdi), %ecx
|
||||
; SSE2-NEXT: andl $3, %eax
|
||||
; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSE2-NEXT: andl $3, %ecx
|
||||
; SSE2-NEXT: movl 8(%rdi), %edx
|
||||
; SSE2-NEXT: andl $3, %edx
|
||||
; SSE2-NEXT: movl 12(%rdi), %esi
|
||||
; SSE2-NEXT: andl $3, %esi
|
||||
; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
||||
; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||
; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
|
||||
@ -743,12 +743,12 @@ define <4 x i32> @mem_shuffle_v4i32_v4i32_xxxx_i32(<4 x i32> %x, i32* %i) nounwi
|
||||
; SSSE3-NEXT: movl (%rdi), %eax
|
||||
; SSSE3-NEXT: movl 4(%rdi), %ecx
|
||||
; SSSE3-NEXT: andl $3, %eax
|
||||
; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSSE3-NEXT: andl $3, %ecx
|
||||
; SSSE3-NEXT: movl 8(%rdi), %edx
|
||||
; SSSE3-NEXT: andl $3, %edx
|
||||
; SSSE3-NEXT: movl 12(%rdi), %esi
|
||||
; SSSE3-NEXT: andl $3, %esi
|
||||
; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
||||
; SSSE3-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||
; SSSE3-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
|
||||
@ -763,12 +763,12 @@ define <4 x i32> @mem_shuffle_v4i32_v4i32_xxxx_i32(<4 x i32> %x, i32* %i) nounwi
|
||||
; SSE41-NEXT: movl (%rdi), %eax
|
||||
; SSE41-NEXT: movl 4(%rdi), %ecx
|
||||
; SSE41-NEXT: andl $3, %eax
|
||||
; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSE41-NEXT: andl $3, %ecx
|
||||
; SSE41-NEXT: movl 8(%rdi), %edx
|
||||
; SSE41-NEXT: andl $3, %edx
|
||||
; SSE41-NEXT: movl 12(%rdi), %esi
|
||||
; SSE41-NEXT: andl $3, %esi
|
||||
; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSE41-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
||||
; SSE41-NEXT: pinsrd $1, -24(%rsp,%rcx,4), %xmm0
|
||||
; SSE41-NEXT: pinsrd $2, -24(%rsp,%rdx,4), %xmm0
|
||||
@ -780,12 +780,12 @@ define <4 x i32> @mem_shuffle_v4i32_v4i32_xxxx_i32(<4 x i32> %x, i32* %i) nounwi
|
||||
; AVX-NEXT: movl (%rdi), %eax
|
||||
; AVX-NEXT: movl 4(%rdi), %ecx
|
||||
; AVX-NEXT: andl $3, %eax
|
||||
; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; AVX-NEXT: andl $3, %ecx
|
||||
; AVX-NEXT: movl 8(%rdi), %edx
|
||||
; AVX-NEXT: andl $3, %edx
|
||||
; AVX-NEXT: movl 12(%rdi), %esi
|
||||
; AVX-NEXT: andl $3, %esi
|
||||
; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
||||
; AVX-NEXT: vpinsrd $1, -24(%rsp,%rcx,4), %xmm0, %xmm0
|
||||
; AVX-NEXT: vpinsrd $2, -24(%rsp,%rdx,4), %xmm0, %xmm0
|
||||
@ -813,68 +813,76 @@ define <4 x i32> @mem_shuffle_v4i32_v4i32_xxxx_i32(<4 x i32> %x, i32* %i) nounwi
|
||||
define <16 x i8> @mem_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8(<16 x i8> %x, i8* %i) nounwind {
|
||||
; SSE2-LABEL: mem_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8:
|
||||
; SSE2: # %bb.0:
|
||||
; SSE2-NEXT: pushq %rbp
|
||||
; SSE2-NEXT: pushq %r15
|
||||
; SSE2-NEXT: pushq %r14
|
||||
; SSE2-NEXT: pushq %r13
|
||||
; SSE2-NEXT: pushq %r12
|
||||
; SSE2-NEXT: pushq %rbx
|
||||
; SSE2-NEXT: movzbl (%rdi), %eax
|
||||
; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSE2-NEXT: movzbl 15(%rdi), %ecx
|
||||
; SSE2-NEXT: andl $15, %ecx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSE2-NEXT: movd %ecx, %xmm8
|
||||
; SSE2-NEXT: movzbl 14(%rdi), %ecx
|
||||
; SSE2-NEXT: andl $15, %ecx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSE2-NEXT: movd %ecx, %xmm15
|
||||
; SSE2-NEXT: movzbl 13(%rdi), %ecx
|
||||
; SSE2-NEXT: andl $15, %ecx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSE2-NEXT: movd %ecx, %xmm9
|
||||
; SSE2-NEXT: movzbl 12(%rdi), %ecx
|
||||
; SSE2-NEXT: andl $15, %ecx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSE2-NEXT: movd %ecx, %xmm3
|
||||
; SSE2-NEXT: movzbl 11(%rdi), %ecx
|
||||
; SSE2-NEXT: andl $15, %ecx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSE2-NEXT: movd %ecx, %xmm10
|
||||
; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
|
||||
; SSE2-NEXT: movzbl 1(%rdi), %r9d
|
||||
; SSE2-NEXT: movzbl 2(%rdi), %r10d
|
||||
; SSE2-NEXT: movzbl 3(%rdi), %r11d
|
||||
; SSE2-NEXT: movzbl 4(%rdi), %r14d
|
||||
; SSE2-NEXT: movzbl 5(%rdi), %r15d
|
||||
; SSE2-NEXT: movzbl 6(%rdi), %r12d
|
||||
; SSE2-NEXT: movzbl 7(%rdi), %r13d
|
||||
; SSE2-NEXT: movzbl 8(%rdi), %ebx
|
||||
; SSE2-NEXT: movzbl 9(%rdi), %r8d
|
||||
; SSE2-NEXT: movzbl 10(%rdi), %ecx
|
||||
; SSE2-NEXT: movzbl 11(%rdi), %edx
|
||||
; SSE2-NEXT: movzbl 12(%rdi), %esi
|
||||
; SSE2-NEXT: movzbl 13(%rdi), %ebp
|
||||
; SSE2-NEXT: movzbl 14(%rdi), %eax
|
||||
; SSE2-NEXT: movzbl 15(%rdi), %edi
|
||||
; SSE2-NEXT: andl $15, %edi
|
||||
; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rdi), %edi
|
||||
; SSE2-NEXT: movd %edi, %xmm8
|
||||
; SSE2-NEXT: andl $15, %eax
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rax), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm15
|
||||
; SSE2-NEXT: andl $15, %ebp
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rbp), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm9
|
||||
; SSE2-NEXT: andl $15, %esi
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rsi), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm3
|
||||
; SSE2-NEXT: andl $15, %edx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rdx), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm10
|
||||
; SSE2-NEXT: andl $15, %ecx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSE2-NEXT: movd %ecx, %xmm7
|
||||
; SSE2-NEXT: movzbl 9(%rdi), %ecx
|
||||
; SSE2-NEXT: andl $15, %ecx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSE2-NEXT: movd %ecx, %xmm11
|
||||
; SSE2-NEXT: movzbl 8(%rdi), %ecx
|
||||
; SSE2-NEXT: andl $15, %ecx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSE2-NEXT: movd %ecx, %xmm6
|
||||
; SSE2-NEXT: movzbl 7(%rdi), %ecx
|
||||
; SSE2-NEXT: andl $15, %ecx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSE2-NEXT: movd %ecx, %xmm12
|
||||
; SSE2-NEXT: movzbl 6(%rdi), %ecx
|
||||
; SSE2-NEXT: andl $15, %ecx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSE2-NEXT: movd %ecx, %xmm5
|
||||
; SSE2-NEXT: movzbl 5(%rdi), %ecx
|
||||
; SSE2-NEXT: andl $15, %ecx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSE2-NEXT: movd %ecx, %xmm13
|
||||
; SSE2-NEXT: movzbl 4(%rdi), %ecx
|
||||
; SSE2-NEXT: andl $15, %ecx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSE2-NEXT: movd %ecx, %xmm4
|
||||
; SSE2-NEXT: movzbl 3(%rdi), %ecx
|
||||
; SSE2-NEXT: andl $15, %ecx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSE2-NEXT: movd %ecx, %xmm14
|
||||
; SSE2-NEXT: movzbl 2(%rdi), %ecx
|
||||
; SSE2-NEXT: andl $15, %ecx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSE2-NEXT: movd %ecx, %xmm1
|
||||
; SSE2-NEXT: movzbl 1(%rdi), %ecx
|
||||
; SSE2-NEXT: andl $15, %ecx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSE2-NEXT: movd %ecx, %xmm2
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rcx), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm7
|
||||
; SSE2-NEXT: andl $15, %r8d
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%r8), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm11
|
||||
; SSE2-NEXT: andl $15, %ebx
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rbx), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm6
|
||||
; SSE2-NEXT: andl $15, %r13d
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%r13), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm12
|
||||
; SSE2-NEXT: andl $15, %r12d
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%r12), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm5
|
||||
; SSE2-NEXT: andl $15, %r15d
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%r15), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm13
|
||||
; SSE2-NEXT: andl $15, %r14d
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%r14), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm4
|
||||
; SSE2-NEXT: andl $15, %r11d
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%r11), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm14
|
||||
; SSE2-NEXT: andl $15, %r10d
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%r10), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm1
|
||||
; SSE2-NEXT: andl $15, %r9d
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%r9), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm2
|
||||
; SSE2-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
|
||||
; SSE2-NEXT: andl $15, %eax
|
||||
; SSE2-NEXT: movzbl -24(%rsp,%rax), %eax
|
||||
; SSE2-NEXT: movd %eax, %xmm0
|
||||
@ -893,72 +901,86 @@ define <16 x i8> @mem_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8(<16 x i8> %x, i8*
|
||||
; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
|
||||
; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
|
||||
; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm6[0]
|
||||
; SSE2-NEXT: popq %rbx
|
||||
; SSE2-NEXT: popq %r12
|
||||
; SSE2-NEXT: popq %r13
|
||||
; SSE2-NEXT: popq %r14
|
||||
; SSE2-NEXT: popq %r15
|
||||
; SSE2-NEXT: popq %rbp
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSSE3-LABEL: mem_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8:
|
||||
; SSSE3: # %bb.0:
|
||||
; SSSE3-NEXT: pushq %rbp
|
||||
; SSSE3-NEXT: pushq %r15
|
||||
; SSSE3-NEXT: pushq %r14
|
||||
; SSSE3-NEXT: pushq %r13
|
||||
; SSSE3-NEXT: pushq %r12
|
||||
; SSSE3-NEXT: pushq %rbx
|
||||
; SSSE3-NEXT: movzbl (%rdi), %eax
|
||||
; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSSE3-NEXT: movzbl 15(%rdi), %ecx
|
||||
; SSSE3-NEXT: andl $15, %ecx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSSE3-NEXT: movd %ecx, %xmm8
|
||||
; SSSE3-NEXT: movzbl 14(%rdi), %ecx
|
||||
; SSSE3-NEXT: andl $15, %ecx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSSE3-NEXT: movd %ecx, %xmm15
|
||||
; SSSE3-NEXT: movzbl 13(%rdi), %ecx
|
||||
; SSSE3-NEXT: andl $15, %ecx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSSE3-NEXT: movd %ecx, %xmm9
|
||||
; SSSE3-NEXT: movzbl 12(%rdi), %ecx
|
||||
; SSSE3-NEXT: andl $15, %ecx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSSE3-NEXT: movd %ecx, %xmm3
|
||||
; SSSE3-NEXT: movzbl 11(%rdi), %ecx
|
||||
; SSSE3-NEXT: andl $15, %ecx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSSE3-NEXT: movd %ecx, %xmm10
|
||||
; SSSE3-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
|
||||
; SSSE3-NEXT: movzbl 1(%rdi), %r9d
|
||||
; SSSE3-NEXT: movzbl 2(%rdi), %r10d
|
||||
; SSSE3-NEXT: movzbl 3(%rdi), %r11d
|
||||
; SSSE3-NEXT: movzbl 4(%rdi), %r14d
|
||||
; SSSE3-NEXT: movzbl 5(%rdi), %r15d
|
||||
; SSSE3-NEXT: movzbl 6(%rdi), %r12d
|
||||
; SSSE3-NEXT: movzbl 7(%rdi), %r13d
|
||||
; SSSE3-NEXT: movzbl 8(%rdi), %ebx
|
||||
; SSSE3-NEXT: movzbl 9(%rdi), %r8d
|
||||
; SSSE3-NEXT: movzbl 10(%rdi), %ecx
|
||||
; SSSE3-NEXT: movzbl 11(%rdi), %edx
|
||||
; SSSE3-NEXT: movzbl 12(%rdi), %esi
|
||||
; SSSE3-NEXT: movzbl 13(%rdi), %ebp
|
||||
; SSSE3-NEXT: movzbl 14(%rdi), %eax
|
||||
; SSSE3-NEXT: movzbl 15(%rdi), %edi
|
||||
; SSSE3-NEXT: andl $15, %edi
|
||||
; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rdi), %edi
|
||||
; SSSE3-NEXT: movd %edi, %xmm8
|
||||
; SSSE3-NEXT: andl $15, %eax
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rax), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm15
|
||||
; SSSE3-NEXT: andl $15, %ebp
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rbp), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm9
|
||||
; SSSE3-NEXT: andl $15, %esi
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rsi), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm3
|
||||
; SSSE3-NEXT: andl $15, %edx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rdx), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm10
|
||||
; SSSE3-NEXT: andl $15, %ecx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSSE3-NEXT: movd %ecx, %xmm7
|
||||
; SSSE3-NEXT: movzbl 9(%rdi), %ecx
|
||||
; SSSE3-NEXT: andl $15, %ecx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSSE3-NEXT: movd %ecx, %xmm11
|
||||
; SSSE3-NEXT: movzbl 8(%rdi), %ecx
|
||||
; SSSE3-NEXT: andl $15, %ecx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSSE3-NEXT: movd %ecx, %xmm6
|
||||
; SSSE3-NEXT: movzbl 7(%rdi), %ecx
|
||||
; SSSE3-NEXT: andl $15, %ecx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSSE3-NEXT: movd %ecx, %xmm12
|
||||
; SSSE3-NEXT: movzbl 6(%rdi), %ecx
|
||||
; SSSE3-NEXT: andl $15, %ecx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSSE3-NEXT: movd %ecx, %xmm5
|
||||
; SSSE3-NEXT: movzbl 5(%rdi), %ecx
|
||||
; SSSE3-NEXT: andl $15, %ecx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSSE3-NEXT: movd %ecx, %xmm13
|
||||
; SSSE3-NEXT: movzbl 4(%rdi), %ecx
|
||||
; SSSE3-NEXT: andl $15, %ecx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSSE3-NEXT: movd %ecx, %xmm4
|
||||
; SSSE3-NEXT: movzbl 3(%rdi), %ecx
|
||||
; SSSE3-NEXT: andl $15, %ecx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSSE3-NEXT: movd %ecx, %xmm14
|
||||
; SSSE3-NEXT: movzbl 2(%rdi), %ecx
|
||||
; SSSE3-NEXT: andl $15, %ecx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSSE3-NEXT: movd %ecx, %xmm1
|
||||
; SSSE3-NEXT: movzbl 1(%rdi), %ecx
|
||||
; SSSE3-NEXT: andl $15, %ecx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rcx), %ecx
|
||||
; SSSE3-NEXT: movd %ecx, %xmm2
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rcx), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm7
|
||||
; SSSE3-NEXT: andl $15, %r8d
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%r8), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm11
|
||||
; SSSE3-NEXT: andl $15, %ebx
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rbx), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm6
|
||||
; SSSE3-NEXT: andl $15, %r13d
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%r13), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm12
|
||||
; SSSE3-NEXT: andl $15, %r12d
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%r12), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm5
|
||||
; SSSE3-NEXT: andl $15, %r15d
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%r15), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm13
|
||||
; SSSE3-NEXT: andl $15, %r14d
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%r14), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm4
|
||||
; SSSE3-NEXT: andl $15, %r11d
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%r11), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm14
|
||||
; SSSE3-NEXT: andl $15, %r10d
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%r10), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm1
|
||||
; SSSE3-NEXT: andl $15, %r9d
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%r9), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm2
|
||||
; SSSE3-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
|
||||
; SSSE3-NEXT: andl $15, %eax
|
||||
; SSSE3-NEXT: movzbl -24(%rsp,%rax), %eax
|
||||
; SSSE3-NEXT: movd %eax, %xmm0
|
||||
@ -977,114 +999,148 @@ define <16 x i8> @mem_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8(<16 x i8> %x, i8*
|
||||
; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
|
||||
; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
|
||||
; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm6[0]
|
||||
; SSSE3-NEXT: popq %rbx
|
||||
; SSSE3-NEXT: popq %r12
|
||||
; SSSE3-NEXT: popq %r13
|
||||
; SSSE3-NEXT: popq %r14
|
||||
; SSSE3-NEXT: popq %r15
|
||||
; SSSE3-NEXT: popq %rbp
|
||||
; SSSE3-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: mem_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8:
|
||||
; SSE41: # %bb.0:
|
||||
; SSE41-NEXT: movzbl (%rdi), %eax
|
||||
; SSE41-NEXT: andl $15, %eax
|
||||
; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSE41-NEXT: movzbl -24(%rsp,%rax), %eax
|
||||
; SSE41-NEXT: movd %eax, %xmm0
|
||||
; SSE41-NEXT: movzbl 1(%rdi), %eax
|
||||
; SSE41-NEXT: andl $15, %eax
|
||||
; SSE41-NEXT: pinsrb $1, -24(%rsp,%rax), %xmm0
|
||||
; SSE41-NEXT: pushq %rbp
|
||||
; SSE41-NEXT: pushq %r15
|
||||
; SSE41-NEXT: pushq %r14
|
||||
; SSE41-NEXT: pushq %r13
|
||||
; SSE41-NEXT: pushq %r12
|
||||
; SSE41-NEXT: pushq %rbx
|
||||
; SSE41-NEXT: movzbl (%rdi), %r9d
|
||||
; SSE41-NEXT: andl $15, %r9d
|
||||
; SSE41-NEXT: movzbl 1(%rdi), %ebx
|
||||
; SSE41-NEXT: movzbl 2(%rdi), %eax
|
||||
; SSE41-NEXT: andl $15, %eax
|
||||
; SSE41-NEXT: pinsrb $2, -24(%rsp,%rax), %xmm0
|
||||
; SSE41-NEXT: movzbl 3(%rdi), %eax
|
||||
; SSE41-NEXT: andl $15, %eax
|
||||
; SSE41-NEXT: pinsrb $3, -24(%rsp,%rax), %xmm0
|
||||
; SSE41-NEXT: movzbl 4(%rdi), %eax
|
||||
; SSE41-NEXT: andl $15, %eax
|
||||
; SSE41-NEXT: pinsrb $4, -24(%rsp,%rax), %xmm0
|
||||
; SSE41-NEXT: movzbl 5(%rdi), %eax
|
||||
; SSE41-NEXT: andl $15, %eax
|
||||
; SSE41-NEXT: pinsrb $5, -24(%rsp,%rax), %xmm0
|
||||
; SSE41-NEXT: movzbl 6(%rdi), %eax
|
||||
; SSE41-NEXT: andl $15, %eax
|
||||
; SSE41-NEXT: pinsrb $6, -24(%rsp,%rax), %xmm0
|
||||
; SSE41-NEXT: movzbl 7(%rdi), %eax
|
||||
; SSE41-NEXT: andl $15, %eax
|
||||
; SSE41-NEXT: pinsrb $7, -24(%rsp,%rax), %xmm0
|
||||
; SSE41-NEXT: movzbl 8(%rdi), %eax
|
||||
; SSE41-NEXT: andl $15, %eax
|
||||
; SSE41-NEXT: pinsrb $8, -24(%rsp,%rax), %xmm0
|
||||
; SSE41-NEXT: movzbl 9(%rdi), %eax
|
||||
; SSE41-NEXT: andl $15, %eax
|
||||
; SSE41-NEXT: pinsrb $9, -24(%rsp,%rax), %xmm0
|
||||
; SSE41-NEXT: movzbl 10(%rdi), %eax
|
||||
; SSE41-NEXT: andl $15, %eax
|
||||
; SSE41-NEXT: pinsrb $10, -24(%rsp,%rax), %xmm0
|
||||
; SSE41-NEXT: movzbl 11(%rdi), %eax
|
||||
; SSE41-NEXT: andl $15, %eax
|
||||
; SSE41-NEXT: pinsrb $11, -24(%rsp,%rax), %xmm0
|
||||
; SSE41-NEXT: movzbl 12(%rdi), %eax
|
||||
; SSE41-NEXT: andl $15, %eax
|
||||
; SSE41-NEXT: pinsrb $12, -24(%rsp,%rax), %xmm0
|
||||
; SSE41-NEXT: movzbl 13(%rdi), %eax
|
||||
; SSE41-NEXT: andl $15, %eax
|
||||
; SSE41-NEXT: pinsrb $13, -24(%rsp,%rax), %xmm0
|
||||
; SSE41-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
|
||||
; SSE41-NEXT: movzbl 3(%rdi), %r11d
|
||||
; SSE41-NEXT: movzbl 4(%rdi), %r14d
|
||||
; SSE41-NEXT: movzbl 5(%rdi), %r15d
|
||||
; SSE41-NEXT: movzbl 6(%rdi), %r12d
|
||||
; SSE41-NEXT: movzbl 7(%rdi), %r13d
|
||||
; SSE41-NEXT: movzbl 8(%rdi), %r10d
|
||||
; SSE41-NEXT: movzbl 9(%rdi), %r8d
|
||||
; SSE41-NEXT: movzbl 10(%rdi), %ecx
|
||||
; SSE41-NEXT: movzbl 11(%rdi), %edx
|
||||
; SSE41-NEXT: movzbl 12(%rdi), %esi
|
||||
; SSE41-NEXT: movzbl 13(%rdi), %ebp
|
||||
; SSE41-NEXT: movzbl 14(%rdi), %eax
|
||||
; SSE41-NEXT: movzbl 15(%rdi), %edi
|
||||
; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; SSE41-NEXT: movzbl -24(%rsp,%r9), %r9d
|
||||
; SSE41-NEXT: movd %r9d, %xmm0
|
||||
; SSE41-NEXT: andl $15, %ebx
|
||||
; SSE41-NEXT: pinsrb $1, -24(%rsp,%rbx), %xmm0
|
||||
; SSE41-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx # 8-byte Reload
|
||||
; SSE41-NEXT: andl $15, %ebx
|
||||
; SSE41-NEXT: pinsrb $2, -24(%rsp,%rbx), %xmm0
|
||||
; SSE41-NEXT: andl $15, %r11d
|
||||
; SSE41-NEXT: pinsrb $3, -24(%rsp,%r11), %xmm0
|
||||
; SSE41-NEXT: andl $15, %r14d
|
||||
; SSE41-NEXT: pinsrb $4, -24(%rsp,%r14), %xmm0
|
||||
; SSE41-NEXT: andl $15, %r15d
|
||||
; SSE41-NEXT: pinsrb $5, -24(%rsp,%r15), %xmm0
|
||||
; SSE41-NEXT: andl $15, %r12d
|
||||
; SSE41-NEXT: pinsrb $6, -24(%rsp,%r12), %xmm0
|
||||
; SSE41-NEXT: andl $15, %r13d
|
||||
; SSE41-NEXT: pinsrb $7, -24(%rsp,%r13), %xmm0
|
||||
; SSE41-NEXT: andl $15, %r10d
|
||||
; SSE41-NEXT: pinsrb $8, -24(%rsp,%r10), %xmm0
|
||||
; SSE41-NEXT: andl $15, %r8d
|
||||
; SSE41-NEXT: pinsrb $9, -24(%rsp,%r8), %xmm0
|
||||
; SSE41-NEXT: andl $15, %ecx
|
||||
; SSE41-NEXT: pinsrb $10, -24(%rsp,%rcx), %xmm0
|
||||
; SSE41-NEXT: andl $15, %edx
|
||||
; SSE41-NEXT: pinsrb $11, -24(%rsp,%rdx), %xmm0
|
||||
; SSE41-NEXT: andl $15, %esi
|
||||
; SSE41-NEXT: pinsrb $12, -24(%rsp,%rsi), %xmm0
|
||||
; SSE41-NEXT: andl $15, %ebp
|
||||
; SSE41-NEXT: pinsrb $13, -24(%rsp,%rbp), %xmm0
|
||||
; SSE41-NEXT: andl $15, %eax
|
||||
; SSE41-NEXT: pinsrb $14, -24(%rsp,%rax), %xmm0
|
||||
; SSE41-NEXT: movzbl 15(%rdi), %eax
|
||||
; SSE41-NEXT: andl $15, %eax
|
||||
; SSE41-NEXT: pinsrb $15, -24(%rsp,%rax), %xmm0
|
||||
; SSE41-NEXT: andl $15, %edi
|
||||
; SSE41-NEXT: pinsrb $15, -24(%rsp,%rdi), %xmm0
|
||||
; SSE41-NEXT: popq %rbx
|
||||
; SSE41-NEXT: popq %r12
|
||||
; SSE41-NEXT: popq %r13
|
||||
; SSE41-NEXT: popq %r14
|
||||
; SSE41-NEXT: popq %r15
|
||||
; SSE41-NEXT: popq %rbp
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: mem_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: movzbl (%rdi), %eax
|
||||
; AVX-NEXT: andl $15, %eax
|
||||
; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; AVX-NEXT: movzbl -24(%rsp,%rax), %eax
|
||||
; AVX-NEXT: vmovd %eax, %xmm0
|
||||
; AVX-NEXT: movzbl 1(%rdi), %eax
|
||||
; AVX-NEXT: andl $15, %eax
|
||||
; AVX-NEXT: vpinsrb $1, -24(%rsp,%rax), %xmm0, %xmm0
|
||||
; AVX-NEXT: pushq %rbp
|
||||
; AVX-NEXT: pushq %r15
|
||||
; AVX-NEXT: pushq %r14
|
||||
; AVX-NEXT: pushq %r13
|
||||
; AVX-NEXT: pushq %r12
|
||||
; AVX-NEXT: pushq %rbx
|
||||
; AVX-NEXT: movzbl (%rdi), %r9d
|
||||
; AVX-NEXT: andl $15, %r9d
|
||||
; AVX-NEXT: movzbl 1(%rdi), %ebx
|
||||
; AVX-NEXT: movzbl 2(%rdi), %eax
|
||||
; AVX-NEXT: andl $15, %eax
|
||||
; AVX-NEXT: vpinsrb $2, -24(%rsp,%rax), %xmm0, %xmm0
|
||||
; AVX-NEXT: movzbl 3(%rdi), %eax
|
||||
; AVX-NEXT: andl $15, %eax
|
||||
; AVX-NEXT: vpinsrb $3, -24(%rsp,%rax), %xmm0, %xmm0
|
||||
; AVX-NEXT: movzbl 4(%rdi), %eax
|
||||
; AVX-NEXT: andl $15, %eax
|
||||
; AVX-NEXT: vpinsrb $4, -24(%rsp,%rax), %xmm0, %xmm0
|
||||
; AVX-NEXT: movzbl 5(%rdi), %eax
|
||||
; AVX-NEXT: andl $15, %eax
|
||||
; AVX-NEXT: vpinsrb $5, -24(%rsp,%rax), %xmm0, %xmm0
|
||||
; AVX-NEXT: movzbl 6(%rdi), %eax
|
||||
; AVX-NEXT: andl $15, %eax
|
||||
; AVX-NEXT: vpinsrb $6, -24(%rsp,%rax), %xmm0, %xmm0
|
||||
; AVX-NEXT: movzbl 7(%rdi), %eax
|
||||
; AVX-NEXT: andl $15, %eax
|
||||
; AVX-NEXT: vpinsrb $7, -24(%rsp,%rax), %xmm0, %xmm0
|
||||
; AVX-NEXT: movzbl 8(%rdi), %eax
|
||||
; AVX-NEXT: andl $15, %eax
|
||||
; AVX-NEXT: vpinsrb $8, -24(%rsp,%rax), %xmm0, %xmm0
|
||||
; AVX-NEXT: movzbl 9(%rdi), %eax
|
||||
; AVX-NEXT: andl $15, %eax
|
||||
; AVX-NEXT: vpinsrb $9, -24(%rsp,%rax), %xmm0, %xmm0
|
||||
; AVX-NEXT: movzbl 10(%rdi), %eax
|
||||
; AVX-NEXT: andl $15, %eax
|
||||
; AVX-NEXT: vpinsrb $10, -24(%rsp,%rax), %xmm0, %xmm0
|
||||
; AVX-NEXT: movzbl 11(%rdi), %eax
|
||||
; AVX-NEXT: andl $15, %eax
|
||||
; AVX-NEXT: vpinsrb $11, -24(%rsp,%rax), %xmm0, %xmm0
|
||||
; AVX-NEXT: movzbl 12(%rdi), %eax
|
||||
; AVX-NEXT: andl $15, %eax
|
||||
; AVX-NEXT: vpinsrb $12, -24(%rsp,%rax), %xmm0, %xmm0
|
||||
; AVX-NEXT: movzbl 13(%rdi), %eax
|
||||
; AVX-NEXT: andl $15, %eax
|
||||
; AVX-NEXT: vpinsrb $13, -24(%rsp,%rax), %xmm0, %xmm0
|
||||
; AVX-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
|
||||
; AVX-NEXT: movzbl 3(%rdi), %r11d
|
||||
; AVX-NEXT: movzbl 4(%rdi), %r14d
|
||||
; AVX-NEXT: movzbl 5(%rdi), %r15d
|
||||
; AVX-NEXT: movzbl 6(%rdi), %r12d
|
||||
; AVX-NEXT: movzbl 7(%rdi), %r13d
|
||||
; AVX-NEXT: movzbl 8(%rdi), %r10d
|
||||
; AVX-NEXT: movzbl 9(%rdi), %r8d
|
||||
; AVX-NEXT: movzbl 10(%rdi), %ecx
|
||||
; AVX-NEXT: movzbl 11(%rdi), %edx
|
||||
; AVX-NEXT: movzbl 12(%rdi), %esi
|
||||
; AVX-NEXT: movzbl 13(%rdi), %ebp
|
||||
; AVX-NEXT: movzbl 14(%rdi), %eax
|
||||
; AVX-NEXT: movzbl 15(%rdi), %edi
|
||||
; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; AVX-NEXT: movzbl -24(%rsp,%r9), %r9d
|
||||
; AVX-NEXT: vmovd %r9d, %xmm0
|
||||
; AVX-NEXT: andl $15, %ebx
|
||||
; AVX-NEXT: vpinsrb $1, -24(%rsp,%rbx), %xmm0, %xmm0
|
||||
; AVX-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rbx # 8-byte Reload
|
||||
; AVX-NEXT: andl $15, %ebx
|
||||
; AVX-NEXT: vpinsrb $2, -24(%rsp,%rbx), %xmm0, %xmm0
|
||||
; AVX-NEXT: andl $15, %r11d
|
||||
; AVX-NEXT: vpinsrb $3, -24(%rsp,%r11), %xmm0, %xmm0
|
||||
; AVX-NEXT: andl $15, %r14d
|
||||
; AVX-NEXT: vpinsrb $4, -24(%rsp,%r14), %xmm0, %xmm0
|
||||
; AVX-NEXT: andl $15, %r15d
|
||||
; AVX-NEXT: vpinsrb $5, -24(%rsp,%r15), %xmm0, %xmm0
|
||||
; AVX-NEXT: andl $15, %r12d
|
||||
; AVX-NEXT: vpinsrb $6, -24(%rsp,%r12), %xmm0, %xmm0
|
||||
; AVX-NEXT: andl $15, %r13d
|
||||
; AVX-NEXT: vpinsrb $7, -24(%rsp,%r13), %xmm0, %xmm0
|
||||
; AVX-NEXT: andl $15, %r10d
|
||||
; AVX-NEXT: vpinsrb $8, -24(%rsp,%r10), %xmm0, %xmm0
|
||||
; AVX-NEXT: andl $15, %r8d
|
||||
; AVX-NEXT: vpinsrb $9, -24(%rsp,%r8), %xmm0, %xmm0
|
||||
; AVX-NEXT: andl $15, %ecx
|
||||
; AVX-NEXT: vpinsrb $10, -24(%rsp,%rcx), %xmm0, %xmm0
|
||||
; AVX-NEXT: andl $15, %edx
|
||||
; AVX-NEXT: vpinsrb $11, -24(%rsp,%rdx), %xmm0, %xmm0
|
||||
; AVX-NEXT: andl $15, %esi
|
||||
; AVX-NEXT: vpinsrb $12, -24(%rsp,%rsi), %xmm0, %xmm0
|
||||
; AVX-NEXT: andl $15, %ebp
|
||||
; AVX-NEXT: vpinsrb $13, -24(%rsp,%rbp), %xmm0, %xmm0
|
||||
; AVX-NEXT: andl $15, %eax
|
||||
; AVX-NEXT: vpinsrb $14, -24(%rsp,%rax), %xmm0, %xmm0
|
||||
; AVX-NEXT: movzbl 15(%rdi), %eax
|
||||
; AVX-NEXT: andl $15, %eax
|
||||
; AVX-NEXT: vpinsrb $15, -24(%rsp,%rax), %xmm0, %xmm0
|
||||
; AVX-NEXT: andl $15, %edi
|
||||
; AVX-NEXT: vpinsrb $15, -24(%rsp,%rdi), %xmm0, %xmm0
|
||||
; AVX-NEXT: popq %rbx
|
||||
; AVX-NEXT: popq %r12
|
||||
; AVX-NEXT: popq %r13
|
||||
; AVX-NEXT: popq %r14
|
||||
; AVX-NEXT: popq %r15
|
||||
; AVX-NEXT: popq %rbp
|
||||
; AVX-NEXT: retq
|
||||
%p0 = getelementptr inbounds i8, i8* %i, i64 0
|
||||
%p1 = getelementptr inbounds i8, i8* %i, i64 1
|
||||
|
||||
@ -189,6 +189,10 @@ define <8 x float> @var_shuffle_v8f32_v8f32_xxxxxxxx_i32(<8 x float> %x, i32 %i0
|
||||
; ALL-NEXT: # kill: def $edx killed $edx def $rdx
|
||||
; ALL-NEXT: # kill: def $esi killed $esi def $rsi
|
||||
; ALL-NEXT: # kill: def $edi killed $edi def $rdi
|
||||
; ALL-NEXT: movl 24(%rbp), %r10d
|
||||
; ALL-NEXT: andl $7, %r10d
|
||||
; ALL-NEXT: movl 16(%rbp), %eax
|
||||
; ALL-NEXT: andl $7, %eax
|
||||
; ALL-NEXT: andl $7, %edi
|
||||
; ALL-NEXT: andl $7, %esi
|
||||
; ALL-NEXT: andl $7, %edx
|
||||
@ -196,10 +200,6 @@ define <8 x float> @var_shuffle_v8f32_v8f32_xxxxxxxx_i32(<8 x float> %x, i32 %i0
|
||||
; ALL-NEXT: andl $7, %r8d
|
||||
; ALL-NEXT: vmovaps %ymm0, (%rsp)
|
||||
; ALL-NEXT: andl $7, %r9d
|
||||
; ALL-NEXT: movl 16(%rbp), %r10d
|
||||
; ALL-NEXT: andl $7, %r10d
|
||||
; ALL-NEXT: movl 24(%rbp), %eax
|
||||
; ALL-NEXT: andl $7, %eax
|
||||
; ALL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
||||
; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
|
||||
; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
|
||||
@ -240,6 +240,10 @@ define <8 x float> @var_shuffle_v8f32_v4f32_xxxxxxxx_i32(<4 x float> %x, i32 %i0
|
||||
; ALL-NEXT: # kill: def $edx killed $edx def $rdx
|
||||
; ALL-NEXT: # kill: def $esi killed $esi def $rsi
|
||||
; ALL-NEXT: # kill: def $edi killed $edi def $rdi
|
||||
; ALL-NEXT: movl {{[0-9]+}}(%rsp), %r10d
|
||||
; ALL-NEXT: andl $3, %r10d
|
||||
; ALL-NEXT: movl {{[0-9]+}}(%rsp), %eax
|
||||
; ALL-NEXT: andl $3, %eax
|
||||
; ALL-NEXT: andl $3, %edi
|
||||
; ALL-NEXT: andl $3, %esi
|
||||
; ALL-NEXT: andl $3, %edx
|
||||
@ -247,10 +251,6 @@ define <8 x float> @var_shuffle_v8f32_v4f32_xxxxxxxx_i32(<4 x float> %x, i32 %i0
|
||||
; ALL-NEXT: andl $3, %r8d
|
||||
; ALL-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp)
|
||||
; ALL-NEXT: andl $3, %r9d
|
||||
; ALL-NEXT: movl {{[0-9]+}}(%rsp), %r10d
|
||||
; ALL-NEXT: andl $3, %r10d
|
||||
; ALL-NEXT: movl {{[0-9]+}}(%rsp), %eax
|
||||
; ALL-NEXT: andl $3, %eax
|
||||
; ALL-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
||||
; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
|
||||
; ALL-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
|
||||
|
||||
@ -19,15 +19,15 @@ define void @update(<5 x i16>* %dst, <5 x i16>* %src, i32 %n) nounwind {
|
||||
; CHECK-NEXT: .p2align 4, 0x90
|
||||
; CHECK-NEXT: .LBB0_2: # %forbody
|
||||
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
|
||||
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
|
||||
; CHECK-NEXT: movslq -{{[0-9]+}}(%rsp), %rcx
|
||||
; CHECK-NEXT: shlq $4, %rcx
|
||||
; CHECK-NEXT: movslq -{{[0-9]+}}(%rsp), %rax
|
||||
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
|
||||
; CHECK-NEXT: shlq $4, %rax
|
||||
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rdx
|
||||
; CHECK-NEXT: movdqa (%rdx,%rcx), %xmm2
|
||||
; CHECK-NEXT: movdqa (%rdx,%rax), %xmm2
|
||||
; CHECK-NEXT: psubw %xmm0, %xmm2
|
||||
; CHECK-NEXT: pmullw %xmm1, %xmm2
|
||||
; CHECK-NEXT: pextrw $4, %xmm2, 8(%rax,%rcx)
|
||||
; CHECK-NEXT: movq %xmm2, (%rax,%rcx)
|
||||
; CHECK-NEXT: pextrw $4, %xmm2, 8(%rcx,%rax)
|
||||
; CHECK-NEXT: movq %xmm2, (%rcx,%rax)
|
||||
; CHECK-NEXT: incl -{{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: .LBB0_1: # %forcond
|
||||
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
|
||||
@ -18,15 +18,15 @@ define void @update(<3 x i32>* %dst, <3 x i32>* %src, i32 %n) nounwind {
|
||||
; CHECK-NEXT: .p2align 4, 0x90
|
||||
; CHECK-NEXT: .LBB0_2: # %forbody
|
||||
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
|
||||
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rax
|
||||
; CHECK-NEXT: movslq -{{[0-9]+}}(%rsp), %rcx
|
||||
; CHECK-NEXT: shlq $4, %rcx
|
||||
; CHECK-NEXT: movslq -{{[0-9]+}}(%rsp), %rax
|
||||
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
|
||||
; CHECK-NEXT: shlq $4, %rax
|
||||
; CHECK-NEXT: movq -{{[0-9]+}}(%rsp), %rdx
|
||||
; CHECK-NEXT: movdqa (%rdx,%rcx), %xmm1
|
||||
; CHECK-NEXT: movdqa (%rdx,%rax), %xmm1
|
||||
; CHECK-NEXT: pslld $2, %xmm1
|
||||
; CHECK-NEXT: psubd %xmm0, %xmm1
|
||||
; CHECK-NEXT: pextrd $2, %xmm1, 8(%rax,%rcx)
|
||||
; CHECK-NEXT: movq %xmm1, (%rax,%rcx)
|
||||
; CHECK-NEXT: pextrd $2, %xmm1, 8(%rcx,%rax)
|
||||
; CHECK-NEXT: movq %xmm1, (%rcx,%rax)
|
||||
; CHECK-NEXT: incl -{{[0-9]+}}(%rsp)
|
||||
; CHECK-NEXT: .LBB0_1: # %forcond
|
||||
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user