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[RISCV] MC layer support for the standard RV64F instruction set extension

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llvm-svn: 320028
This commit is contained in:
Alex Bradbury 2017-12-07 11:02:55 +00:00
parent a2dbb084dc
commit 8a323d4ed8
4 changed files with 70 additions and 0 deletions
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22
lib/Target/RISCV/RISCVInstrInfoF.td
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@ -165,3 +165,25 @@ def FMV_W_X : FPUnaryOp_r<0b1111000, 0b000, FPR32, GPR, "fmv.w.x"> {
let rs2 = 0b00000;
}
} // Predicates = [HasStdExtF]
let Predicates = [HasStdExtF, IsRV64] in {
def FCVT_L_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.l.s"> {
let rs2 = 0b00010;
}
def : FPUnaryOpDynFrmAlias<FCVT_L_S, "fcvt.l.s", GPR, FPR32>;
def FCVT_LU_S : FPUnaryOp_r_frm<0b1100000, GPR, FPR32, "fcvt.lu.s"> {
let rs2 = 0b00011;
}
def : FPUnaryOpDynFrmAlias<FCVT_LU_S, "fcvt.lu.s", GPR, FPR32>;
def FCVT_S_L : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.l"> {
let rs2 = 0b00010;
}
def : FPUnaryOpDynFrmAlias<FCVT_S_L, "fcvt.s.l", FPR32, GPR>;
def FCVT_S_LU : FPUnaryOp_r_frm<0b1101000, FPR32, GPR, "fcvt.s.lu"> {
let rs2 = 0b00011;
}
def : FPUnaryOpDynFrmAlias<FCVT_S_LU, "fcvt.s.lu", FPR32, GPR>;
} // Predicates = [HasStdExtF, IsRV64]

2
test/MC/RISCV/rv32f-invalid.s
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@ -30,3 +30,5 @@ fnmsub.s f18, f19, f20, f21, 0b111 # CHECK: :[[@LINE]]:30: error: operand must b
# Using 'D' instructions for an 'F'-only target
fadd.d ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
# Using RV64F instructions for RV32 is tested in rv64f-valid.s

9
test/MC/RISCV/rv64f-invalid.s Normal file
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@ -0,0 +1,9 @@
# RUN: not llvm-mc -triple riscv64 -mattr=+f < %s 2>&1 | FileCheck %s
# Integer registers where FP regs are expected
fcvt.l.s ft0, a0 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
fcvt.lu.s ft1, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
# FP registers where integer regs are expected
fcvt.s.l a2, ft2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
fcvt.s.lu a3, ft3 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction

37
test/MC/RISCV/rv64f-valid.s Normal file
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@ -0,0 +1,37 @@
# RUN: llvm-mc %s -triple=riscv64 -mattr=+f -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
# RUN: | llvm-objdump -mattr=+f -d - | FileCheck -check-prefix=CHECK-INST %s
# RUN: not llvm-mc -triple riscv32 -mattr=+f < %s 2>&1 \
# RUN: | FileCheck -check-prefix=CHECK-RV32 %s
# CHECK-INST: fcvt.l.s a0, ft0
# CHECK: encoding: [0x53,0x75,0x20,0xc0]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled
fcvt.l.s a0, ft0
# CHECK-INST: fcvt.lu.s a1, ft1
# CHECK: encoding: [0xd3,0xf5,0x30,0xc0]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled
fcvt.lu.s a1, ft1
# CHECK-INST: fcvt.s.l ft2, a2
# CHECK: encoding: [0x53,0x71,0x26,0xd0]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled
fcvt.s.l ft2, a2
# CHECK-INST: fcvt.s.lu ft3, a3
# CHECK: encoding: [0xd3,0xf1,0x36,0xd0]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled
fcvt.s.lu ft3, a3
# Rounding modes
# CHECK-INST: fcvt.l.s a4, ft4, rne
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled
fcvt.l.s a4, ft4, rne
# CHECK-INST: fcvt.lu.s a5, ft5, rtz
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled
fcvt.lu.s a5, ft5, rtz
# CHECK-INST: fcvt.s.l ft6, a6, rdn
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled
fcvt.s.l ft6, a6, rdn
# CHECK-INST: fcvt.s.lu ft7, a7, rup
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled
fcvt.s.lu ft7, a7, rup