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https://github.com/RPCS3/llvm-mirror.git
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[SimpleLoopUnswitch] Implement handling of prof branch_weights metadata for SwitchInst
Differential Revision: https://reviews.llvm.org/D60606 llvm-svn: 364734
This commit is contained in:
Yevgeny Rouban
parent
5f8f6e4068
commit
8a7c3670e1
@ -594,11 +594,13 @@ static bool unswitchTrivialSwitch(Loop &L, SwitchInst &SI, DominatorTree &DT,
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ExitCaseIndices.push_back(Case.getCaseIndex());
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}
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BasicBlock *DefaultExitBB = nullptr;
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SwitchInstProfUpdateWrapper::CaseWeightOpt DefaultCaseWeight =
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SwitchInstProfUpdateWrapper::getSuccessorWeight(SI, 0);
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if (!L.contains(SI.getDefaultDest()) &&
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areLoopExitPHIsLoopInvariant(L, *ParentBB, *SI.getDefaultDest()) &&
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!isa<UnreachableInst>(SI.getDefaultDest()->getTerminator()))
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!isa<UnreachableInst>(SI.getDefaultDest()->getTerminator())) {
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DefaultExitBB = SI.getDefaultDest();
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else if (ExitCaseIndices.empty())
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} else if (ExitCaseIndices.empty())
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return false;
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LLVM_DEBUG(dbgs() << " unswitching trivial switch...\n");
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@ -622,8 +624,11 @@ static bool unswitchTrivialSwitch(Loop &L, SwitchInst &SI, DominatorTree &DT,
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// Store the exit cases into a separate data structure and remove them from
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// the switch.
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SmallVector<std::pair<ConstantInt *, BasicBlock *>, 4> ExitCases;
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SmallVector<std::tuple<ConstantInt *, BasicBlock *,
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SwitchInstProfUpdateWrapper::CaseWeightOpt>,
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4> ExitCases;
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ExitCases.reserve(ExitCaseIndices.size());
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SwitchInstProfUpdateWrapper SIW(SI);
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// We walk the case indices backwards so that we remove the last case first
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// and don't disrupt the earlier indices.
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for (unsigned Index : reverse(ExitCaseIndices)) {
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@ -633,9 +638,10 @@ static bool unswitchTrivialSwitch(Loop &L, SwitchInst &SI, DominatorTree &DT,
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if (!ExitL || ExitL->contains(OuterL))
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OuterL = ExitL;
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// Save the value of this case.
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ExitCases.push_back({CaseI->getCaseValue(), CaseI->getCaseSuccessor()});
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auto W = SIW.getSuccessorWeight(CaseI->getSuccessorIndex());
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ExitCases.emplace_back(CaseI->getCaseValue(), CaseI->getCaseSuccessor(), W);
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// Delete the unswitched cases.
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SI.removeCase(CaseI);
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SIW.removeCase(CaseI);
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}
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if (SE) {
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@ -673,6 +679,7 @@ static bool unswitchTrivialSwitch(Loop &L, SwitchInst &SI, DominatorTree &DT,
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// Now add the unswitched switch.
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auto *NewSI = SwitchInst::Create(LoopCond, NewPH, ExitCases.size(), OldPH);
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SwitchInstProfUpdateWrapper NewSIW(*NewSI);
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// Rewrite the IR for the unswitched basic blocks. This requires two steps.
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// First, we split any exit blocks with remaining in-loop predecessors. Then
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@ -700,9 +707,9 @@ static bool unswitchTrivialSwitch(Loop &L, SwitchInst &SI, DominatorTree &DT,
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}
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// Note that we must use a reference in the for loop so that we update the
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// container.
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for (auto &CasePair : reverse(ExitCases)) {
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for (auto &ExitCase : reverse(ExitCases)) {
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// Grab a reference to the exit block in the pair so that we can update it.
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BasicBlock *ExitBB = CasePair.second;
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BasicBlock *ExitBB = std::get<1>(ExitCase);
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// If this case is the last edge into the exit block, we can simply reuse it
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// as it will no longer be a loop exit. No mapping necessary.
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@ -724,27 +731,39 @@ static bool unswitchTrivialSwitch(Loop &L, SwitchInst &SI, DominatorTree &DT,
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/*FullUnswitch*/ true);
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}
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// Update the case pair to point to the split block.
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CasePair.second = SplitExitBB;
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std::get<1>(ExitCase) = SplitExitBB;
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}
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// Now add the unswitched cases. We do this in reverse order as we built them
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// in reverse order.
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for (auto CasePair : reverse(ExitCases)) {
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ConstantInt *CaseVal = CasePair.first;
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BasicBlock *UnswitchedBB = CasePair.second;
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for (auto &ExitCase : reverse(ExitCases)) {
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ConstantInt *CaseVal = std::get<0>(ExitCase);
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BasicBlock *UnswitchedBB = std::get<1>(ExitCase);
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NewSI->addCase(CaseVal, UnswitchedBB);
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NewSIW.addCase(CaseVal, UnswitchedBB, std::get<2>(ExitCase));
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}
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// If the default was unswitched, re-point it and add explicit cases for
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// entering the loop.
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if (DefaultExitBB) {
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NewSI->setDefaultDest(DefaultExitBB);
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NewSIW->setDefaultDest(DefaultExitBB);
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NewSIW.setSuccessorWeight(0, DefaultCaseWeight);
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// We removed all the exit cases, so we just copy the cases to the
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// unswitched switch.
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for (auto Case : SI.cases())
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NewSI->addCase(Case.getCaseValue(), NewPH);
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for (const auto &Case : SI.cases())
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NewSIW.addCase(Case.getCaseValue(), NewPH,
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SIW.getSuccessorWeight(Case.getSuccessorIndex()));
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} else if (DefaultCaseWeight) {
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// We have to set branch weight of the default case.
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uint64_t SW = *DefaultCaseWeight;
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for (const auto &Case : SI.cases()) {
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auto W = SIW.getSuccessorWeight(Case.getSuccessorIndex());
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assert(W &&
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"case weight must be defined as default case weight is defined");
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SW += *W;
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}
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NewSIW.setSuccessorWeight(0, SW);
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}
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// If we ended up with a common successor for every path through the switch
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@ -769,7 +788,7 @@ static bool unswitchTrivialSwitch(Loop &L, SwitchInst &SI, DominatorTree &DT,
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/*KeepOneInputPHIs*/ true);
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}
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// Now nuke the switch and replace it with a direct branch.
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SI.eraseFromParent();
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SIW.eraseFromParent();
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BranchInst::Create(CommonSuccBB, BB);
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} else if (DefaultExitBB) {
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assert(SI.getNumCases() > 0 &&
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@ -779,8 +798,11 @@ static bool unswitchTrivialSwitch(Loop &L, SwitchInst &SI, DominatorTree &DT,
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// being simple and keeping the number of edges from this switch to
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// successors the same, and avoiding any PHI update complexity.
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auto LastCaseI = std::prev(SI.case_end());
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SI.setDefaultDest(LastCaseI->getCaseSuccessor());
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SI.removeCase(LastCaseI);
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SIW.setSuccessorWeight(
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0, SIW.getSuccessorWeight(LastCaseI->getSuccessorIndex()));
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SIW.removeCase(LastCaseI);
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}
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// Walk the unswitched exit blocks and the unswitched split blocks and update
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34
test/Transforms/SimpleLoopUnswitch/basictest-profmd.ll
Normal file
34
test/Transforms/SimpleLoopUnswitch/basictest-profmd.ll
Normal file
@ -0,0 +1,34 @@
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; RUN: opt -passes='loop(unswitch),verify<loops>' -S < %s | FileCheck %s
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; RUN: opt -enable-mssa-loop-dependency=true -verify-memoryssa -passes='loop(unswitch),verify<loops>' -S < %s | FileCheck %s
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declare void @incf()
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declare void @decf()
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define i32 @test2(i32 %c) {
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; CHECK-LABEL: @test2(
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br label %loop_begin
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; CHECK: !prof ![[MD0:[0-9]+]]
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; CHECK: loop_begin:
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; CHECK: !prof ![[MD1:[0-9]+]]
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loop_begin:
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switch i32 %c, label %default [
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i32 1, label %inc
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i32 2, label %dec
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], !prof !{!"branch_weights", i32 99, i32 1, i32 2}
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inc:
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call void @incf()
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br label %loop_begin
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dec:
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call void @decf()
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br label %loop_begin
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default:
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ret i32 0
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}
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; CHECK: ![[MD0]] = !{!"branch_weights", i32 99, i32 1, i32 2}
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; CHECK: ![[MD1]] = !{!"branch_weights", i32 2, i32 1}
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228
test/Transforms/SimpleLoopUnswitch/trivial-unswitch-profmd.ll
Normal file
228
test/Transforms/SimpleLoopUnswitch/trivial-unswitch-profmd.ll
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@ -0,0 +1,228 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; then metadata checks MDn were added manually.
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; RUN: opt -passes='loop(unswitch),verify<loops>' -S < %s | FileCheck %s
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; RUN: opt -enable-mssa-loop-dependency=true -verify-memoryssa -passes='loop(unswitch),verify<loops>' -S < %s | FileCheck %s
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declare void @some_func()
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; Test for a trivially unswitchable switch with non-default case exiting.
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define i32 @test2(i32* %var, i32 %cond1, i32 %cond2) {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i32 [[COND2:%.*]], label [[ENTRY_SPLIT:%.*]] [
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; CHECK-NEXT: i32 2, label [[LOOP_EXIT2:%.*]]
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; CHECK-NEXT: ], !prof ![[MD0:[0-9]+]]
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; CHECK: entry.split:
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; CHECK-NEXT: br label [[LOOP_BEGIN:%.*]]
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; CHECK: loop_begin:
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; CHECK-NEXT: [[VAR_VAL:%.*]] = load i32, i32* [[VAR:%.*]]
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; CHECK-NEXT: switch i32 [[COND2]], label [[LOOP2:%.*]] [
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; CHECK-NEXT: i32 0, label [[LOOP0:%.*]]
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; CHECK-NEXT: i32 1, label [[LOOP1:%.*]]
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; CHECK-NEXT: ], !prof ![[MD1:[0-9]+]]
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; CHECK: loop0:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH:%.*]]
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; CHECK: loop1:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop2:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop_latch:
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; CHECK-NEXT: br label [[LOOP_BEGIN]]
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; CHECK: loop_exit1:
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; CHECK-NEXT: ret i32 0
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; CHECK: loop_exit2:
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; CHECK-NEXT: ret i32 0
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; CHECK: loop_exit3:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %loop_begin
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loop_begin:
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%var_val = load i32, i32* %var
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switch i32 %cond2, label %loop2 [
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i32 0, label %loop0
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i32 1, label %loop1
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i32 2, label %loop_exit2
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], !prof !{!"branch_weights", i32 99, i32 100, i32 101, i32 102}
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loop0:
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call void @some_func()
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br label %loop_latch
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loop1:
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call void @some_func()
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br label %loop_latch
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loop2:
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call void @some_func()
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br label %loop_latch
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loop_latch:
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br label %loop_begin
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loop_exit1:
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ret i32 0
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loop_exit2:
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ret i32 0
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loop_exit3:
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ret i32 0
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}
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; Test for a trivially unswitchable switch with only the default case exiting.
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define i32 @test3(i32* %var, i32 %cond1, i32 %cond2) {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i32 [[COND2:%.*]], label [[LOOP_EXIT2:%.*]] [
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; CHECK-NEXT: i32 0, label [[ENTRY_SPLIT:%.*]]
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; CHECK-NEXT: i32 1, label [[ENTRY_SPLIT]]
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; CHECK-NEXT: i32 2, label [[ENTRY_SPLIT]]
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; CHECK-NEXT: ], !prof ![[MD2:[0-9]+]]
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; CHECK: entry.split:
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; CHECK-NEXT: br label [[LOOP_BEGIN:%.*]]
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; CHECK: loop_begin:
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; CHECK-NEXT: [[VAR_VAL:%.*]] = load i32, i32* [[VAR:%.*]]
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; CHECK-NEXT: switch i32 [[COND2]], label [[LOOP2:%.*]] [
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; CHECK-NEXT: i32 0, label [[LOOP0:%.*]]
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; CHECK-NEXT: i32 1, label [[LOOP1:%.*]]
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; CHECK-NEXT: ], !prof ![[MD3:[0-9]+]]
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; CHECK: loop0:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH:%.*]]
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; CHECK: loop1:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop2:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop_latch:
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; CHECK-NEXT: br label [[LOOP_BEGIN]]
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; CHECK: loop_exit1:
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; CHECK-NEXT: ret i32 0
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; CHECK: loop_exit2:
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; CHECK-NEXT: ret i32 0
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; CHECK: loop_exit3:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %loop_begin
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loop_begin:
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%var_val = load i32, i32* %var
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switch i32 %cond2, label %loop_exit2 [
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i32 0, label %loop0
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i32 1, label %loop1
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i32 2, label %loop2
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], !prof !{!"branch_weights", i32 99, i32 100, i32 101, i32 102}
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loop0:
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call void @some_func()
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br label %loop_latch
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loop1:
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call void @some_func()
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br label %loop_latch
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loop2:
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call void @some_func()
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br label %loop_latch
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loop_latch:
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br label %loop_begin
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loop_exit1:
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ret i32 0
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loop_exit2:
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ret i32 0
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loop_exit3:
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ret i32 0
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}
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; Test for a trivially unswitchable switch with multiple exiting cases and
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; multiple looping cases.
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define i32 @test4(i32* %var, i32 %cond1, i32 %cond2) {
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; CHECK-LABEL: @test4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: switch i32 [[COND2:%.*]], label [[LOOP_EXIT2:%.*]] [
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; CHECK-NEXT: i32 13, label [[LOOP_EXIT1:%.*]]
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; CHECK-NEXT: i32 42, label [[LOOP_EXIT3:%.*]]
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; CHECK-NEXT: i32 0, label [[ENTRY_SPLIT:%.*]]
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; CHECK-NEXT: i32 1, label [[ENTRY_SPLIT]]
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; CHECK-NEXT: i32 2, label [[ENTRY_SPLIT]]
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; CHECK-NEXT: ], !prof ![[MD4:[0-9]+]]
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; CHECK: entry.split:
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; CHECK-NEXT: br label [[LOOP_BEGIN:%.*]]
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; CHECK: loop_begin:
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; CHECK-NEXT: [[VAR_VAL:%.*]] = load i32, i32* [[VAR:%.*]]
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; CHECK-NEXT: switch i32 [[COND2]], label [[LOOP2:%.*]] [
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; CHECK-NEXT: i32 0, label [[LOOP0:%.*]]
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; CHECK-NEXT: i32 1, label [[LOOP1:%.*]]
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; CHECK-NEXT: ], !prof ![[MD3:[0-9]+]]
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; CHECK: loop0:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH:%.*]]
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; CHECK: loop1:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop2:
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; CHECK-NEXT: call void @some_func()
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; CHECK-NEXT: br label [[LOOP_LATCH]]
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; CHECK: loop_latch:
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; CHECK-NEXT: br label [[LOOP_BEGIN]]
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; CHECK: loop_exit1:
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; CHECK-NEXT: ret i32 0
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; CHECK: loop_exit2:
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; CHECK-NEXT: ret i32 0
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; CHECK: loop_exit3:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %loop_begin
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loop_begin:
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%var_val = load i32, i32* %var
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switch i32 %cond2, label %loop_exit2 [
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i32 0, label %loop0
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i32 1, label %loop1
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i32 13, label %loop_exit1
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i32 2, label %loop2
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i32 42, label %loop_exit3
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], !prof !{!"branch_weights", i32 99, i32 100, i32 101, i32 113, i32 102, i32 142}
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loop0:
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call void @some_func()
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br label %loop_latch
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loop1:
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call void @some_func()
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br label %loop_latch
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loop2:
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call void @some_func()
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br label %loop_latch
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loop_latch:
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br label %loop_begin
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loop_exit1:
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ret i32 0
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loop_exit2:
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ret i32 0
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loop_exit3:
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ret i32 0
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}
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; CHECK: ![[MD0]] = !{!"branch_weights", i32 300, i32 102}
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; CHECK: ![[MD1]] = !{!"branch_weights", i32 99, i32 100, i32 101}
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; CHECK: ![[MD2]] = !{!"branch_weights", i32 99, i32 100, i32 101, i32 102}
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; CHECK: ![[MD3]] = !{!"branch_weights", i32 102, i32 100, i32 101}
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; CHECK: ![[MD4]] = !{!"branch_weights", i32 99, i32 113, i32 142, i32 100, i32 101, i32 102}
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