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https://github.com/RPCS3/llvm-mirror.git
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Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMem
to IntrReadWriteArgMem, as it's for reading as well as writing. llvm-svn: 110395
This commit is contained in:
Dan Gohman
parent
a26a97510a
commit
8a813c4ded
@ -19,10 +19,11 @@ include "llvm/CodeGen/ValueTypes.td"
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class IntrinsicProperty;
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// Intr*Mem - Memory properties. An intrinsic is allowed to have exactly one of
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// Intr*Mem - Memory properties. An intrinsic is allowed to have at most one of
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// these properties set. They are listed from the most aggressive (best to use
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// if correct) to the least aggressive. If no property is set, the worst case
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// is assumed (IntrWriteMem).
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// is assumed (it may read and write any memory it can get access to and it may
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// have other side effects).
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// IntrNoMem - The intrinsic does not access memory or have any other side
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// effects. It may be CSE'd deleted if dead, etc.
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@ -37,15 +38,11 @@ def IntrReadArgMem : IntrinsicProperty;
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// deleted if dead.
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def IntrReadMem : IntrinsicProperty;
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// IntrWriteArgMem - This intrinsic reads and writes only from memory that one
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// of its arguments points to, but may access an unspecified amount. The reads
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// and writes may be volatile, but except for this it has no other side effects.
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def IntrWriteArgMem : IntrinsicProperty;
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// IntrWriteMem - This intrinsic may read or modify unspecified memory or has
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// other side effects. It cannot be modified by the optimizer. This is the
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// default if the intrinsic has no other Intr*Mem property.
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def IntrWriteMem : IntrinsicProperty;
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// IntrReadWriteArgMem - This intrinsic reads and writes only from memory that
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// one of its arguments points to, but may access an unspecified amount. The
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// reads and writes may be volatile, but except for this it has no other side
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// effects.
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def IntrReadWriteArgMem : IntrinsicProperty;
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// Commutative - This intrinsic is commutative: X op Y == Y op X.
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def Commutative : IntrinsicProperty;
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@ -190,7 +187,7 @@ def int_gcread : Intrinsic<[llvm_ptr_ty],
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[IntrReadArgMem]>;
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def int_gcwrite : Intrinsic<[],
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[llvm_ptr_ty, llvm_ptr_ty, llvm_ptrptr_ty],
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[IntrWriteArgMem, NoCapture<1>, NoCapture<2>]>;
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[IntrReadWriteArgMem, NoCapture<1>, NoCapture<2>]>;
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//===--------------------- Code Generator Intrinsics ----------------------===//
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//
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@ -204,21 +201,19 @@ def int_stacksave : Intrinsic<[llvm_ptr_ty]>,
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def int_stackrestore : Intrinsic<[], [llvm_ptr_ty]>,
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GCCBuiltin<"__builtin_stack_restore">;
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// IntrWriteArgMem is more pessimistic than strictly necessary for prefetch,
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// IntrReadWriteArgMem is more pessimistic than strictly necessary for prefetch,
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// however it does conveniently prevent the prefetch from being reordered
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// with respect to nearby accesses to the same memory.
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def int_prefetch : Intrinsic<[],
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[llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrWriteArgMem, NoCapture<0>]>;
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[IntrReadWriteArgMem, NoCapture<0>]>;
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def int_pcmarker : Intrinsic<[], [llvm_i32_ty]>;
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def int_readcyclecounter : Intrinsic<[llvm_i64_ty]>;
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// Stack Protector Intrinsic - The stackprotector intrinsic writes the stack
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// guard to the correct place on the stack frame.
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def int_stackprotector : Intrinsic<[],
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[llvm_ptr_ty, llvm_ptrptr_ty],
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[IntrWriteMem]>;
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def int_stackprotector : Intrinsic<[], [llvm_ptr_ty, llvm_ptrptr_ty], []>;
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//===------------------- Standard C Library Intrinsics --------------------===//
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//
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@ -226,15 +221,15 @@ def int_stackprotector : Intrinsic<[],
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def int_memcpy : Intrinsic<[],
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[llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty,
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llvm_i32_ty, llvm_i1_ty],
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[IntrWriteArgMem, NoCapture<0>, NoCapture<1>]>;
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[IntrReadWriteArgMem, NoCapture<0>, NoCapture<1>]>;
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def int_memmove : Intrinsic<[],
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[llvm_anyptr_ty, llvm_anyptr_ty, llvm_anyint_ty,
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llvm_i32_ty, llvm_i1_ty],
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[IntrWriteArgMem, NoCapture<0>, NoCapture<1>]>;
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[IntrReadWriteArgMem, NoCapture<0>, NoCapture<1>]>;
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def int_memset : Intrinsic<[],
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[llvm_anyptr_ty, llvm_i8_ty, llvm_anyint_ty,
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llvm_i32_ty, llvm_i1_ty],
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[IntrWriteArgMem, NoCapture<0>]>;
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[IntrReadWriteArgMem, NoCapture<0>]>;
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// These functions do not actually read memory, but they are sensitive to the
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// rounding mode. This needs to be modelled separately; in the meantime
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@ -331,7 +326,7 @@ def int_annotation : Intrinsic<[llvm_anyint_ty],
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//
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def int_init_trampoline : Intrinsic<[llvm_ptr_ty],
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[llvm_ptr_ty, llvm_ptr_ty, llvm_ptr_ty],
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[IntrWriteArgMem]>,
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[IntrReadWriteArgMem]>,
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GCCBuiltin<"__builtin_init_trampoline">;
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//===------------------------ Overflow Intrinsics -------------------------===//
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@ -369,79 +364,79 @@ def int_memory_barrier : Intrinsic<[],
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def int_atomic_cmp_swap : Intrinsic<[llvm_anyint_ty],
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[LLVMAnyPointerType<LLVMMatchType<0>>,
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LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrWriteArgMem, NoCapture<0>]>,
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[IntrReadWriteArgMem, NoCapture<0>]>,
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GCCBuiltin<"__sync_val_compare_and_swap">;
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def int_atomic_load_add : Intrinsic<[llvm_anyint_ty],
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[LLVMAnyPointerType<LLVMMatchType<0>>,
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LLVMMatchType<0>],
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[IntrWriteArgMem, NoCapture<0>]>,
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[IntrReadWriteArgMem, NoCapture<0>]>,
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GCCBuiltin<"__sync_fetch_and_add">;
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def int_atomic_swap : Intrinsic<[llvm_anyint_ty],
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[LLVMAnyPointerType<LLVMMatchType<0>>,
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LLVMMatchType<0>],
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[IntrWriteArgMem, NoCapture<0>]>,
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[IntrReadWriteArgMem, NoCapture<0>]>,
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GCCBuiltin<"__sync_lock_test_and_set">;
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def int_atomic_load_sub : Intrinsic<[llvm_anyint_ty],
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[LLVMAnyPointerType<LLVMMatchType<0>>,
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LLVMMatchType<0>],
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[IntrWriteArgMem, NoCapture<0>]>,
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[IntrReadWriteArgMem, NoCapture<0>]>,
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GCCBuiltin<"__sync_fetch_and_sub">;
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def int_atomic_load_and : Intrinsic<[llvm_anyint_ty],
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[LLVMAnyPointerType<LLVMMatchType<0>>,
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LLVMMatchType<0>],
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[IntrWriteArgMem, NoCapture<0>]>,
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[IntrReadWriteArgMem, NoCapture<0>]>,
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GCCBuiltin<"__sync_fetch_and_and">;
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def int_atomic_load_or : Intrinsic<[llvm_anyint_ty],
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[LLVMAnyPointerType<LLVMMatchType<0>>,
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LLVMMatchType<0>],
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[IntrWriteArgMem, NoCapture<0>]>,
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[IntrReadWriteArgMem, NoCapture<0>]>,
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GCCBuiltin<"__sync_fetch_and_or">;
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def int_atomic_load_xor : Intrinsic<[llvm_anyint_ty],
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[LLVMAnyPointerType<LLVMMatchType<0>>,
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LLVMMatchType<0>],
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[IntrWriteArgMem, NoCapture<0>]>,
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[IntrReadWriteArgMem, NoCapture<0>]>,
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GCCBuiltin<"__sync_fetch_and_xor">;
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def int_atomic_load_nand : Intrinsic<[llvm_anyint_ty],
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[LLVMAnyPointerType<LLVMMatchType<0>>,
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LLVMMatchType<0>],
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[IntrWriteArgMem, NoCapture<0>]>,
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[IntrReadWriteArgMem, NoCapture<0>]>,
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GCCBuiltin<"__sync_fetch_and_nand">;
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def int_atomic_load_min : Intrinsic<[llvm_anyint_ty],
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[LLVMAnyPointerType<LLVMMatchType<0>>,
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LLVMMatchType<0>],
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[IntrWriteArgMem, NoCapture<0>]>,
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[IntrReadWriteArgMem, NoCapture<0>]>,
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GCCBuiltin<"__sync_fetch_and_min">;
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def int_atomic_load_max : Intrinsic<[llvm_anyint_ty],
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[LLVMAnyPointerType<LLVMMatchType<0>>,
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LLVMMatchType<0>],
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[IntrWriteArgMem, NoCapture<0>]>,
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[IntrReadWriteArgMem, NoCapture<0>]>,
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GCCBuiltin<"__sync_fetch_and_max">;
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def int_atomic_load_umin : Intrinsic<[llvm_anyint_ty],
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[LLVMAnyPointerType<LLVMMatchType<0>>,
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LLVMMatchType<0>],
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[IntrWriteArgMem, NoCapture<0>]>,
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[IntrReadWriteArgMem, NoCapture<0>]>,
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GCCBuiltin<"__sync_fetch_and_umin">;
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def int_atomic_load_umax : Intrinsic<[llvm_anyint_ty],
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[LLVMAnyPointerType<LLVMMatchType<0>>,
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LLVMMatchType<0>],
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[IntrWriteArgMem, NoCapture<0>]>,
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[IntrReadWriteArgMem, NoCapture<0>]>,
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GCCBuiltin<"__sync_fetch_and_umax">;
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//===------------------------- Memory Use Markers -------------------------===//
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//
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def int_lifetime_start : Intrinsic<[],
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[llvm_i64_ty, llvm_ptr_ty],
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[IntrWriteArgMem, NoCapture<1>]>;
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[IntrReadWriteArgMem, NoCapture<1>]>;
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def int_lifetime_end : Intrinsic<[],
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[llvm_i64_ty, llvm_ptr_ty],
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[IntrWriteArgMem, NoCapture<1>]>;
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[IntrReadWriteArgMem, NoCapture<1>]>;
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def int_invariant_start : Intrinsic<[llvm_descriptor_ty],
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[llvm_i64_ty, llvm_ptr_ty],
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[IntrReadArgMem, NoCapture<1>]>;
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def int_invariant_end : Intrinsic<[],
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[llvm_descriptor_ty, llvm_i64_ty,
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llvm_ptr_ty],
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[IntrWriteArgMem, NoCapture<2>]>;
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[IntrReadWriteArgMem, NoCapture<2>]>;
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//===-------------------------- Other Intrinsics --------------------------===//
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//
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@ -42,7 +42,7 @@ let TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.".
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def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
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Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
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def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
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Intrinsic<[], [llvm_i32_ty], [IntrWriteMem]>;
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Intrinsic<[], [llvm_i32_ty], []>;
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def int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
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[IntrNoMem]>;
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def int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
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@ -375,31 +375,31 @@ let TargetPrefix = "arm" in {
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// Interleaving vector stores from N-element structures.
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def int_arm_neon_vst1 : Intrinsic<[],
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[llvm_ptr_ty, llvm_anyvector_ty],
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[IntrWriteArgMem]>;
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[IntrReadWriteArgMem]>;
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def int_arm_neon_vst2 : Intrinsic<[],
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[llvm_ptr_ty, llvm_anyvector_ty,
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LLVMMatchType<0>], [IntrWriteArgMem]>;
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LLVMMatchType<0>], [IntrReadWriteArgMem]>;
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def int_arm_neon_vst3 : Intrinsic<[],
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[llvm_ptr_ty, llvm_anyvector_ty,
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LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrWriteArgMem]>;
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[IntrReadWriteArgMem]>;
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def int_arm_neon_vst4 : Intrinsic<[],
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[llvm_ptr_ty, llvm_anyvector_ty,
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LLVMMatchType<0>, LLVMMatchType<0>,
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LLVMMatchType<0>], [IntrWriteArgMem]>;
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LLVMMatchType<0>], [IntrReadWriteArgMem]>;
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// Vector store N-element structure from one lane.
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def int_arm_neon_vst2lane : Intrinsic<[],
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[llvm_ptr_ty, llvm_anyvector_ty,
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LLVMMatchType<0>, llvm_i32_ty],
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[IntrWriteArgMem]>;
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[IntrReadWriteArgMem]>;
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def int_arm_neon_vst3lane : Intrinsic<[],
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[llvm_ptr_ty, llvm_anyvector_ty,
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LLVMMatchType<0>, LLVMMatchType<0>,
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llvm_i32_ty], [IntrWriteArgMem]>;
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llvm_i32_ty], [IntrReadWriteArgMem]>;
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def int_arm_neon_vst4lane : Intrinsic<[],
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[llvm_ptr_ty, llvm_anyvector_ty,
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LLVMMatchType<0>, LLVMMatchType<0>,
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LLVMMatchType<0>, llvm_i32_ty],
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[IntrWriteArgMem]>;
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[IntrReadWriteArgMem]>;
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}
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@ -18,17 +18,17 @@
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// Non-altivec intrinsics.
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let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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// dcba/dcbf/dcbi/dcbst/dcbt/dcbz/dcbzl(PPC970) instructions.
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def int_ppc_dcba : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
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def int_ppc_dcbf : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
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def int_ppc_dcbi : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
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def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
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def int_ppc_dcbt : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
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def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
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def int_ppc_dcbz : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
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def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
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def int_ppc_dcba : Intrinsic<[], [llvm_ptr_ty], []>;
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def int_ppc_dcbf : Intrinsic<[], [llvm_ptr_ty], []>;
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def int_ppc_dcbi : Intrinsic<[], [llvm_ptr_ty], []>;
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def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>;
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def int_ppc_dcbt : Intrinsic<[], [llvm_ptr_ty], []>;
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def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty], []>;
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def int_ppc_dcbz : Intrinsic<[], [llvm_ptr_ty], []>;
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def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
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// sync instruction
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def int_ppc_sync : Intrinsic<[], [], [IntrWriteMem]>;
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def int_ppc_sync : Intrinsic<[], [], []>;
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}
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@ -86,31 +86,31 @@ class PowerPC_Vec_WWW_Intrinsic<string GCCIntSuffix>
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let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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// Data Stream Control.
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def int_ppc_altivec_dss : GCCBuiltin<"__builtin_altivec_dss">,
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Intrinsic<[], [llvm_i32_ty], [IntrWriteMem]>;
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Intrinsic<[], [llvm_i32_ty], []>;
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def int_ppc_altivec_dssall : GCCBuiltin<"__builtin_altivec_dssall">,
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Intrinsic<[], [], [IntrWriteMem]>;
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Intrinsic<[], [], []>;
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def int_ppc_altivec_dst : GCCBuiltin<"__builtin_altivec_dst">,
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Intrinsic<[],
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[llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrWriteMem]>;
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[]>;
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def int_ppc_altivec_dstt : GCCBuiltin<"__builtin_altivec_dstt">,
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Intrinsic<[],
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[llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrWriteMem]>;
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[]>;
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def int_ppc_altivec_dstst : GCCBuiltin<"__builtin_altivec_dstst">,
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Intrinsic<[],
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[llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrWriteMem]>;
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[]>;
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def int_ppc_altivec_dststt : GCCBuiltin<"__builtin_altivec_dststt">,
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Intrinsic<[],
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[llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrWriteMem]>;
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[]>;
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// VSCR access.
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def int_ppc_altivec_mfvscr : GCCBuiltin<"__builtin_altivec_mfvscr">,
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Intrinsic<[llvm_v8i16_ty], [], [IntrReadMem]>;
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def int_ppc_altivec_mtvscr : GCCBuiltin<"__builtin_altivec_mtvscr">,
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Intrinsic<[], [llvm_v4i32_ty], [IntrWriteMem]>;
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Intrinsic<[], [llvm_v4i32_ty], []>;
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// Loads. These don't map directly to GCC builtins because they represent the
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@ -129,20 +129,15 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
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// Stores. These don't map directly to GCC builtins because they represent the
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// source address with a single pointer.
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def int_ppc_altivec_stvx :
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Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
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[IntrWriteMem]>;
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Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty], []>;
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def int_ppc_altivec_stvxl :
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Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
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[IntrWriteMem]>;
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Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty], []>;
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def int_ppc_altivec_stvebx :
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Intrinsic<[], [llvm_v16i8_ty, llvm_ptr_ty],
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[IntrWriteMem]>;
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Intrinsic<[], [llvm_v16i8_ty, llvm_ptr_ty], []>;
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def int_ppc_altivec_stvehx :
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Intrinsic<[], [llvm_v8i16_ty, llvm_ptr_ty],
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[IntrWriteMem]>;
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Intrinsic<[], [llvm_v8i16_ty, llvm_ptr_ty], []>;
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def int_ppc_altivec_stvewx :
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Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty],
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[IntrWriteMem]>;
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Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty], []>;
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// Comparisons setting a vector.
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def int_ppc_altivec_vcmpbfp : GCCBuiltin<"__builtin_altivec_vcmpbfp">,
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@ -143,24 +143,24 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse_storeu_ps : GCCBuiltin<"__builtin_ia32_storeups">,
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Intrinsic<[], [llvm_ptr_ty,
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llvm_v4f32_ty], [IntrWriteMem]>;
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llvm_v4f32_ty], []>;
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}
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// Cacheability support ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">,
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Intrinsic<[], [llvm_ptr_ty,
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llvm_v4f32_ty], [IntrWriteMem]>;
|
||||
llvm_v4f32_ty], []>;
|
||||
def int_x86_sse_sfence : GCCBuiltin<"__builtin_ia32_sfence">,
|
||||
Intrinsic<[], [], [IntrWriteMem]>;
|
||||
Intrinsic<[], [], []>;
|
||||
}
|
||||
|
||||
// Control register.
|
||||
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
def int_x86_sse_stmxcsr :
|
||||
Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
|
||||
Intrinsic<[], [llvm_ptr_ty], []>;
|
||||
def int_x86_sse_ldmxcsr :
|
||||
Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
|
||||
Intrinsic<[], [llvm_ptr_ty], []>;
|
||||
}
|
||||
|
||||
// Misc.
|
||||
@ -459,26 +459,26 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
def int_x86_sse2_storeu_pd : GCCBuiltin<"__builtin_ia32_storeupd">,
|
||||
Intrinsic<[], [llvm_ptr_ty,
|
||||
llvm_v2f64_ty], [IntrWriteMem]>;
|
||||
llvm_v2f64_ty], []>;
|
||||
def int_x86_sse2_storeu_dq : GCCBuiltin<"__builtin_ia32_storedqu">,
|
||||
Intrinsic<[], [llvm_ptr_ty,
|
||||
llvm_v16i8_ty], [IntrWriteMem]>;
|
||||
llvm_v16i8_ty], []>;
|
||||
def int_x86_sse2_storel_dq : GCCBuiltin<"__builtin_ia32_storelv4si">,
|
||||
Intrinsic<[], [llvm_ptr_ty,
|
||||
llvm_v4i32_ty], [IntrWriteMem]>;
|
||||
llvm_v4i32_ty], []>;
|
||||
}
|
||||
|
||||
// Cacheability support ops
|
||||
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
def int_x86_sse2_movnt_dq : GCCBuiltin<"__builtin_ia32_movntdq">,
|
||||
Intrinsic<[], [llvm_ptr_ty,
|
||||
llvm_v2i64_ty], [IntrWriteMem]>;
|
||||
llvm_v2i64_ty], []>;
|
||||
def int_x86_sse2_movnt_pd : GCCBuiltin<"__builtin_ia32_movntpd">,
|
||||
Intrinsic<[], [llvm_ptr_ty,
|
||||
llvm_v2f64_ty], [IntrWriteMem]>;
|
||||
llvm_v2f64_ty], []>;
|
||||
def int_x86_sse2_movnt_i : GCCBuiltin<"__builtin_ia32_movnti">,
|
||||
Intrinsic<[], [llvm_ptr_ty,
|
||||
llvm_i32_ty], [IntrWriteMem]>;
|
||||
llvm_i32_ty], []>;
|
||||
}
|
||||
|
||||
// Misc.
|
||||
@ -498,13 +498,13 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
Intrinsic<[llvm_i32_ty], [llvm_v16i8_ty], [IntrNoMem]>;
|
||||
def int_x86_sse2_maskmov_dqu : GCCBuiltin<"__builtin_ia32_maskmovdqu">,
|
||||
Intrinsic<[], [llvm_v16i8_ty,
|
||||
llvm_v16i8_ty, llvm_ptr_ty], [IntrWriteMem]>;
|
||||
llvm_v16i8_ty, llvm_ptr_ty], []>;
|
||||
def int_x86_sse2_clflush : GCCBuiltin<"__builtin_ia32_clflush">,
|
||||
Intrinsic<[], [llvm_ptr_ty], [IntrWriteMem]>;
|
||||
Intrinsic<[], [llvm_ptr_ty], []>;
|
||||
def int_x86_sse2_lfence : GCCBuiltin<"__builtin_ia32_lfence">,
|
||||
Intrinsic<[], [], [IntrWriteMem]>;
|
||||
Intrinsic<[], [], []>;
|
||||
def int_x86_sse2_mfence : GCCBuiltin<"__builtin_ia32_mfence">,
|
||||
Intrinsic<[], [], [IntrWriteMem]>;
|
||||
Intrinsic<[], [], []>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -546,10 +546,10 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
def int_x86_sse3_monitor : GCCBuiltin<"__builtin_ia32_monitor">,
|
||||
Intrinsic<[], [llvm_ptr_ty,
|
||||
llvm_i32_ty, llvm_i32_ty], [IntrWriteMem]>;
|
||||
llvm_i32_ty, llvm_i32_ty], []>;
|
||||
def int_x86_sse3_mwait : GCCBuiltin<"__builtin_ia32_mwait">,
|
||||
Intrinsic<[], [llvm_i32_ty,
|
||||
llvm_i32_ty], [IntrWriteMem]>;
|
||||
llvm_i32_ty], []>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -1363,21 +1363,21 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
// SIMD store ops
|
||||
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
def int_x86_avx_storeu_pd_256 : GCCBuiltin<"__builtin_ia32_storeupd256">,
|
||||
Intrinsic<[], [llvm_ptr_ty, llvm_v4f64_ty], [IntrWriteMem]>;
|
||||
Intrinsic<[], [llvm_ptr_ty, llvm_v4f64_ty], []>;
|
||||
def int_x86_avx_storeu_ps_256 : GCCBuiltin<"__builtin_ia32_storeups256">,
|
||||
Intrinsic<[], [llvm_ptr_ty, llvm_v8f32_ty], [IntrWriteMem]>;
|
||||
Intrinsic<[], [llvm_ptr_ty, llvm_v8f32_ty], []>;
|
||||
def int_x86_avx_storeu_dq_256 : GCCBuiltin<"__builtin_ia32_storedqu256">,
|
||||
Intrinsic<[], [llvm_ptr_ty, llvm_v32i8_ty], [IntrWriteMem]>;
|
||||
Intrinsic<[], [llvm_ptr_ty, llvm_v32i8_ty], []>;
|
||||
}
|
||||
|
||||
// Cacheability support ops
|
||||
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
def int_x86_avx_movnt_dq_256 : GCCBuiltin<"__builtin_ia32_movntdq256">,
|
||||
Intrinsic<[], [llvm_ptr_ty, llvm_v4i64_ty], [IntrWriteMem]>;
|
||||
Intrinsic<[], [llvm_ptr_ty, llvm_v4i64_ty], []>;
|
||||
def int_x86_avx_movnt_pd_256 : GCCBuiltin<"__builtin_ia32_movntpd256">,
|
||||
Intrinsic<[], [llvm_ptr_ty, llvm_v4f64_ty], [IntrWriteMem]>;
|
||||
Intrinsic<[], [llvm_ptr_ty, llvm_v4f64_ty], []>;
|
||||
def int_x86_avx_movnt_ps_256 : GCCBuiltin<"__builtin_ia32_movntps256">,
|
||||
Intrinsic<[], [llvm_ptr_ty, llvm_v8f32_ty], [IntrWriteMem]>;
|
||||
Intrinsic<[], [llvm_ptr_ty, llvm_v8f32_ty], []>;
|
||||
}
|
||||
|
||||
// Conditional load ops
|
||||
@ -1396,18 +1396,18 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
def int_x86_avx_maskstore_pd : GCCBuiltin<"__builtin_ia32_maskstorepd">,
|
||||
Intrinsic<[], [llvm_ptr_ty,
|
||||
llvm_v2f64_ty, llvm_v2f64_ty], [IntrWriteMem]>;
|
||||
llvm_v2f64_ty, llvm_v2f64_ty], []>;
|
||||
def int_x86_avx_maskstore_ps : GCCBuiltin<"__builtin_ia32_maskstoreps">,
|
||||
Intrinsic<[], [llvm_ptr_ty,
|
||||
llvm_v4f32_ty, llvm_v4f32_ty], [IntrWriteMem]>;
|
||||
llvm_v4f32_ty, llvm_v4f32_ty], []>;
|
||||
def int_x86_avx_maskstore_pd_256 :
|
||||
GCCBuiltin<"__builtin_ia32_maskstorepd256">,
|
||||
Intrinsic<[], [llvm_ptr_ty,
|
||||
llvm_v4f64_ty, llvm_v4f64_ty], [IntrWriteMem]>;
|
||||
llvm_v4f64_ty, llvm_v4f64_ty], []>;
|
||||
def int_x86_avx_maskstore_ps_256 :
|
||||
GCCBuiltin<"__builtin_ia32_maskstoreps256">,
|
||||
Intrinsic<[], [llvm_ptr_ty,
|
||||
llvm_v8f32_ty, llvm_v8f32_ty], [IntrWriteMem]>;
|
||||
llvm_v8f32_ty, llvm_v8f32_ty], []>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -1416,9 +1416,9 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
// Empty MMX state op.
|
||||
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
def int_x86_mmx_emms : GCCBuiltin<"__builtin_ia32_emms">,
|
||||
Intrinsic<[], [], [IntrWriteMem]>;
|
||||
Intrinsic<[], [], []>;
|
||||
def int_x86_mmx_femms : GCCBuiltin<"__builtin_ia32_femms">,
|
||||
Intrinsic<[], [], [IntrWriteMem]>;
|
||||
Intrinsic<[], [], []>;
|
||||
}
|
||||
|
||||
// Integer arithmetic ops.
|
||||
@ -1594,14 +1594,11 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
// Misc.
|
||||
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
|
||||
def int_x86_mmx_maskmovq : GCCBuiltin<"__builtin_ia32_maskmovq">,
|
||||
Intrinsic<[],
|
||||
[llvm_v8i8_ty, llvm_v8i8_ty, llvm_ptr_ty],
|
||||
[IntrWriteMem]>;
|
||||
Intrinsic<[], [llvm_v8i8_ty, llvm_v8i8_ty, llvm_ptr_ty], []>;
|
||||
|
||||
def int_x86_mmx_pmovmskb : GCCBuiltin<"__builtin_ia32_pmovmskb">,
|
||||
Intrinsic<[llvm_i32_ty], [llvm_v8i8_ty], [IntrNoMem]>;
|
||||
|
||||
def int_x86_mmx_movnt_dq : GCCBuiltin<"__builtin_ia32_movntq">,
|
||||
Intrinsic<[], [llvm_ptr_ty,
|
||||
llvm_v1i64_ty], [IntrWriteMem]>;
|
||||
Intrinsic<[], [llvm_ptr_ty, llvm_v1i64_ty], []>;
|
||||
}
|
||||
|
||||
@ -17,17 +17,11 @@
|
||||
|
||||
// MBlaze intrinsic classes.
|
||||
let TargetPrefix = "mblaze", isTarget = 1 in {
|
||||
class MBFSL_Get_Intrinsic : Intrinsic<[llvm_i32_ty],
|
||||
[llvm_i32_ty],
|
||||
[IntrWriteMem]>;
|
||||
class MBFSL_Get_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], []>;
|
||||
|
||||
class MBFSL_Put_Intrinsic : Intrinsic<[],
|
||||
[llvm_i32_ty, llvm_i32_ty],
|
||||
[IntrWriteMem]>;
|
||||
class MBFSL_Put_Intrinsic : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty], []>;
|
||||
|
||||
class MBFSL_PutT_Intrinsic : Intrinsic<[],
|
||||
[llvm_i32_ty],
|
||||
[IntrWriteMem]>;
|
||||
class MBFSL_PutT_Intrinsic : Intrinsic<[], [llvm_i32_ty], []>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -2197,10 +2197,10 @@ private:
|
||||
if (IntInfo->ModRef >= CodeGenIntrinsic::ReadArgMem)
|
||||
mayLoad = true;// These may load memory.
|
||||
|
||||
if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem)
|
||||
if (IntInfo->ModRef >= CodeGenIntrinsic::ReadWriteArgMem)
|
||||
mayStore = true;// Intrinsics that can write to memory are 'mayStore'.
|
||||
|
||||
if (IntInfo->ModRef >= CodeGenIntrinsic::WriteMem)
|
||||
if (IntInfo->ModRef >= CodeGenIntrinsic::ReadWriteMem)
|
||||
// WriteMem intrinsics can have other strange effects.
|
||||
HasSideEffects = true;
|
||||
}
|
||||
|
||||
@ -60,7 +60,7 @@ namespace llvm {
|
||||
|
||||
// Memory mod/ref behavior of this intrinsic.
|
||||
enum {
|
||||
NoMem, ReadArgMem, ReadMem, WriteArgMem, WriteMem
|
||||
NoMem, ReadArgMem, ReadMem, ReadWriteArgMem, ReadWriteMem
|
||||
} ModRef;
|
||||
|
||||
/// This is set to true if the intrinsic is overloaded by its argument
|
||||
|
||||
@ -434,7 +434,7 @@ std::vector<CodeGenIntrinsic> llvm::LoadIntrinsics(const RecordKeeper &RC,
|
||||
CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
|
||||
TheDef = R;
|
||||
std::string DefName = R->getName();
|
||||
ModRef = WriteMem;
|
||||
ModRef = ReadWriteMem;
|
||||
isOverloaded = false;
|
||||
isCommutative = false;
|
||||
|
||||
@ -555,10 +555,8 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) {
|
||||
ModRef = ReadArgMem;
|
||||
else if (Property->getName() == "IntrReadMem")
|
||||
ModRef = ReadMem;
|
||||
else if (Property->getName() == "IntrWriteArgMem")
|
||||
ModRef = WriteArgMem;
|
||||
else if (Property->getName() == "IntrWriteMem")
|
||||
ModRef = WriteMem;
|
||||
else if (Property->getName() == "IntrReadWriteArgMem")
|
||||
ModRef = ReadWriteArgMem;
|
||||
else if (Property->getName() == "Commutative")
|
||||
isCommutative = true;
|
||||
else if (Property->isSubClassOf("NoCapture")) {
|
||||
|
||||
@ -545,7 +545,7 @@ EmitModRefBehavior(const std::vector<CodeGenIntrinsic> &Ints, raw_ostream &OS){
|
||||
OS << "switch (iid) {\n";
|
||||
OS << "default:\n return UnknownModRefBehavior;\n";
|
||||
for (unsigned i = 0, e = Ints.size(); i != e; ++i) {
|
||||
if (Ints[i].ModRef == CodeGenIntrinsic::WriteMem)
|
||||
if (Ints[i].ModRef == CodeGenIntrinsic::ReadWriteMem)
|
||||
continue;
|
||||
OS << "case " << TargetPrefix << "Intrinsic::" << Ints[i].EnumName
|
||||
<< ":\n";
|
||||
@ -559,7 +559,7 @@ EmitModRefBehavior(const std::vector<CodeGenIntrinsic> &Ints, raw_ostream &OS){
|
||||
case CodeGenIntrinsic::ReadMem:
|
||||
OS << " return OnlyReadsMemory;\n";
|
||||
break;
|
||||
case CodeGenIntrinsic::WriteArgMem:
|
||||
case CodeGenIntrinsic::ReadWriteArgMem:
|
||||
OS << " return AccessesArguments;\n";
|
||||
break;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user