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[SLP] Add support for commutative icmp/fcmp predicates
For the cases where the icmp/fcmp predicate is commutative, use reorderInputsAccordingToOpcode to collect and commute the operands. This requires a helper to recognise commutativity in both general Instruction and CmpInstr types - the CmpInst::isCommutative doesn't overload the Instruction::isCommutative method for reasons I'm not clear on (maybe because its based on predicate not opcode?!?). Differential Revision: https://reviews.llvm.org/D59992 llvm-svn: 357266
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Simon Pilgrim
parent
d1644d3934
commit
8a9486eaf0
@ -206,6 +206,13 @@ static bool isSplat(ArrayRef<Value *> VL) {
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return true;
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}
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/// \returns True if \p I is commutative, handles CmpInst as well as Instruction.
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static bool isCommutative(Instruction *I) {
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if (auto *IC = dyn_cast<CmpInst>(I))
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return IC->isCommutative();
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return I->isCommutative();
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}
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/// Checks if the vector of instructions can be represented as a shuffle, like:
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/// %x0 = extractelement <4 x i8> %x, i32 0
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/// %x3 = extractelement <4 x i8> %x, i32 3
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@ -1854,16 +1861,23 @@ void BoUpSLP::buildTree_rec(ArrayRef<Value *> VL, unsigned Depth,
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newTreeEntry(VL, true, UserTreeIdx, ReuseShuffleIndicies);
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LLVM_DEBUG(dbgs() << "SLP: added a vector of compares.\n");
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// Collect operands - commute if it uses the swapped predicate.
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ValueList Left, Right;
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for (Value *V : VL) {
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auto *Cmp = cast<CmpInst>(V);
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Value *LHS = Cmp->getOperand(0);
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Value *RHS = Cmp->getOperand(1);
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if (Cmp->getPredicate() != P0)
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std::swap(LHS, RHS);
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Left.push_back(LHS);
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Right.push_back(RHS);
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if (cast<CmpInst>(VL0)->isCommutative()) {
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// Commutative predicate - collect + sort operands of the instructions
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// so that each side is more likely to have the same opcode.
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assert(P0 == SwapP0 && "Commutative Predicate mismatch");
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reorderInputsAccordingToOpcode(S, VL, Left, Right);
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} else {
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// Collect operands - commute if it uses the swapped predicate.
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for (Value *V : VL) {
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auto *Cmp = cast<CmpInst>(V);
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Value *LHS = Cmp->getOperand(0);
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Value *RHS = Cmp->getOperand(1);
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if (Cmp->getPredicate() != P0)
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std::swap(LHS, RHS);
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Left.push_back(LHS);
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Right.push_back(RHS);
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}
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}
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UserTreeIdx.EdgeIdx = 0;
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@ -2884,7 +2898,7 @@ void BoUpSLP::reorderInputsAccordingToOpcode(const InstructionsState &S,
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Instruction *I = cast<Instruction>(VL[i]);
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// Commute to favor either a splat or maximizing having the same opcodes on
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// one side.
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if (I->isCommutative() &&
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if (isCommutative(I) &&
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shouldReorderOperands(i, Left, Right, AllSameOpcodeLeft,
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AllSameOpcodeRight, SplatLeft, SplatRight))
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std::swap(Left[i], Right[i]);
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@ -2925,11 +2939,11 @@ void BoUpSLP::reorderInputsAccordingToOpcode(const InstructionsState &S,
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if (isConsecutiveAccess(L, L1, *DL, *SE)) {
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auto *VL1 = cast<Instruction>(VL[j]);
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auto *VL2 = cast<Instruction>(VL[j + 1]);
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if (VL2->isCommutative()) {
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if (isCommutative(VL2)) {
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std::swap(Left[j + 1], Right[j + 1]);
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continue;
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}
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if (VL1->isCommutative()) {
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if (isCommutative(VL1)) {
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std::swap(Left[j], Right[j]);
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continue;
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}
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@ -2941,11 +2955,11 @@ void BoUpSLP::reorderInputsAccordingToOpcode(const InstructionsState &S,
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if (isConsecutiveAccess(L, L1, *DL, *SE)) {
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auto *VL1 = cast<Instruction>(VL[j]);
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auto *VL2 = cast<Instruction>(VL[j + 1]);
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if (VL2->isCommutative()) {
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if (isCommutative(VL2)) {
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std::swap(Left[j + 1], Right[j + 1]);
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continue;
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}
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if (VL1->isCommutative()) {
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if (isCommutative(VL1)) {
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std::swap(Left[j], Right[j]);
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continue;
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}
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@ -8,26 +8,10 @@
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define <4 x i32> @icmp_eq_v4i32(<4 x i32> %a, i32* %b) {
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; CHECK-LABEL: @icmp_eq_v4i32(
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; CHECK-NEXT: [[A0:%.*]] = extractelement <4 x i32> [[A:%.*]], i32 0
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; CHECK-NEXT: [[A1:%.*]] = extractelement <4 x i32> [[A]], i32 1
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; CHECK-NEXT: [[A2:%.*]] = extractelement <4 x i32> [[A]], i32 2
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; CHECK-NEXT: [[A3:%.*]] = extractelement <4 x i32> [[A]], i32 3
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; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i64 1
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; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 2
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; CHECK-NEXT: [[P3:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 3
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; CHECK-NEXT: [[B0:%.*]] = load i32, i32* [[B]], align 4
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; CHECK-NEXT: [[B1:%.*]] = load i32, i32* [[P1]], align 4
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; CHECK-NEXT: [[B2:%.*]] = load i32, i32* [[P2]], align 4
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; CHECK-NEXT: [[B3:%.*]] = load i32, i32* [[P3]], align 4
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; CHECK-NEXT: [[C0:%.*]] = icmp eq i32 [[A0]], [[B0]]
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; CHECK-NEXT: [[C1:%.*]] = icmp eq i32 [[B1]], [[A1]]
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; CHECK-NEXT: [[C2:%.*]] = icmp eq i32 [[B2]], [[A2]]
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; CHECK-NEXT: [[C3:%.*]] = icmp eq i32 [[A3]], [[B3]]
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; CHECK-NEXT: [[D0:%.*]] = insertelement <4 x i1> undef, i1 [[C0]], i32 0
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; CHECK-NEXT: [[D1:%.*]] = insertelement <4 x i1> [[D0]], i1 [[C1]], i32 1
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; CHECK-NEXT: [[D2:%.*]] = insertelement <4 x i1> [[D1]], i1 [[C2]], i32 2
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; CHECK-NEXT: [[D3:%.*]] = insertelement <4 x i1> [[D2]], i1 [[C3]], i32 3
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; CHECK-NEXT: [[R:%.*]] = sext <4 x i1> [[D3]] to <4 x i32>
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[B:%.*]] to <4 x i32>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <4 x i32> [[TMP2]], [[A:%.*]]
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; CHECK-NEXT: [[R:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> [[R]]
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;
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%a0 = extractelement <4 x i32> %a, i32 0
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@ -56,26 +40,10 @@ define <4 x i32> @icmp_eq_v4i32(<4 x i32> %a, i32* %b) {
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define <4 x i32> @icmp_ne_v4i32(<4 x i32> %a, i32* %b) {
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; CHECK-LABEL: @icmp_ne_v4i32(
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; CHECK-NEXT: [[A0:%.*]] = extractelement <4 x i32> [[A:%.*]], i32 0
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; CHECK-NEXT: [[A1:%.*]] = extractelement <4 x i32> [[A]], i32 1
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; CHECK-NEXT: [[A2:%.*]] = extractelement <4 x i32> [[A]], i32 2
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; CHECK-NEXT: [[A3:%.*]] = extractelement <4 x i32> [[A]], i32 3
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; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i64 1
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; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 2
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; CHECK-NEXT: [[P3:%.*]] = getelementptr inbounds i32, i32* [[B]], i64 3
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; CHECK-NEXT: [[B0:%.*]] = load i32, i32* [[B]], align 4
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; CHECK-NEXT: [[B1:%.*]] = load i32, i32* [[P1]], align 4
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; CHECK-NEXT: [[B2:%.*]] = load i32, i32* [[P2]], align 4
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; CHECK-NEXT: [[B3:%.*]] = load i32, i32* [[P3]], align 4
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; CHECK-NEXT: [[C0:%.*]] = icmp ne i32 [[A0]], [[B0]]
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; CHECK-NEXT: [[C1:%.*]] = icmp ne i32 [[B1]], [[A1]]
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; CHECK-NEXT: [[C2:%.*]] = icmp ne i32 [[B2]], [[A2]]
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; CHECK-NEXT: [[C3:%.*]] = icmp ne i32 [[A3]], [[B3]]
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; CHECK-NEXT: [[D0:%.*]] = insertelement <4 x i1> undef, i1 [[C0]], i32 0
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; CHECK-NEXT: [[D1:%.*]] = insertelement <4 x i1> [[D0]], i1 [[C1]], i32 1
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; CHECK-NEXT: [[D2:%.*]] = insertelement <4 x i1> [[D1]], i1 [[C2]], i32 2
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; CHECK-NEXT: [[D3:%.*]] = insertelement <4 x i1> [[D2]], i1 [[C3]], i32 3
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; CHECK-NEXT: [[R:%.*]] = sext <4 x i1> [[D3]] to <4 x i32>
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[B:%.*]] to <4 x i32>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, <4 x i32>* [[TMP1]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i32> [[TMP2]], [[A:%.*]]
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; CHECK-NEXT: [[R:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> [[R]]
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;
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%a0 = extractelement <4 x i32> %a, i32 0
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@ -104,26 +72,10 @@ define <4 x i32> @icmp_ne_v4i32(<4 x i32> %a, i32* %b) {
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define <4 x i32> @fcmp_oeq_v4i32(<4 x float> %a, float* %b) {
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; CHECK-LABEL: @fcmp_oeq_v4i32(
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; CHECK-NEXT: [[A0:%.*]] = extractelement <4 x float> [[A:%.*]], i32 0
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; CHECK-NEXT: [[A1:%.*]] = extractelement <4 x float> [[A]], i32 1
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; CHECK-NEXT: [[A2:%.*]] = extractelement <4 x float> [[A]], i32 2
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; CHECK-NEXT: [[A3:%.*]] = extractelement <4 x float> [[A]], i32 3
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; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds float, float* [[B:%.*]], i64 1
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; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds float, float* [[B]], i64 2
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; CHECK-NEXT: [[P3:%.*]] = getelementptr inbounds float, float* [[B]], i64 3
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; CHECK-NEXT: [[B0:%.*]] = load float, float* [[B]], align 4
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; CHECK-NEXT: [[B1:%.*]] = load float, float* [[P1]], align 4
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; CHECK-NEXT: [[B2:%.*]] = load float, float* [[P2]], align 4
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; CHECK-NEXT: [[B3:%.*]] = load float, float* [[P3]], align 4
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; CHECK-NEXT: [[C0:%.*]] = fcmp oeq float [[A0]], [[B0]]
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; CHECK-NEXT: [[C1:%.*]] = fcmp oeq float [[B1]], [[A1]]
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; CHECK-NEXT: [[C2:%.*]] = fcmp oeq float [[B2]], [[A2]]
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; CHECK-NEXT: [[C3:%.*]] = fcmp oeq float [[A3]], [[B3]]
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; CHECK-NEXT: [[D0:%.*]] = insertelement <4 x i1> undef, i1 [[C0]], i32 0
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; CHECK-NEXT: [[D1:%.*]] = insertelement <4 x i1> [[D0]], i1 [[C1]], i32 1
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; CHECK-NEXT: [[D2:%.*]] = insertelement <4 x i1> [[D1]], i1 [[C2]], i32 2
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; CHECK-NEXT: [[D3:%.*]] = insertelement <4 x i1> [[D2]], i1 [[C3]], i32 3
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; CHECK-NEXT: [[R:%.*]] = sext <4 x i1> [[D3]] to <4 x i32>
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[B:%.*]] to <4 x float>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = fcmp oeq <4 x float> [[TMP2]], [[A:%.*]]
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; CHECK-NEXT: [[R:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> [[R]]
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;
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%a0 = extractelement <4 x float> %a, i32 0
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@ -152,26 +104,10 @@ define <4 x i32> @fcmp_oeq_v4i32(<4 x float> %a, float* %b) {
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define <4 x i32> @fcmp_uno_v4i32(<4 x float> %a, float* %b) {
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; CHECK-LABEL: @fcmp_uno_v4i32(
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; CHECK-NEXT: [[A0:%.*]] = extractelement <4 x float> [[A:%.*]], i32 0
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; CHECK-NEXT: [[A1:%.*]] = extractelement <4 x float> [[A]], i32 1
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; CHECK-NEXT: [[A2:%.*]] = extractelement <4 x float> [[A]], i32 2
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; CHECK-NEXT: [[A3:%.*]] = extractelement <4 x float> [[A]], i32 3
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; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds float, float* [[B:%.*]], i64 1
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; CHECK-NEXT: [[P2:%.*]] = getelementptr inbounds float, float* [[B]], i64 2
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; CHECK-NEXT: [[P3:%.*]] = getelementptr inbounds float, float* [[B]], i64 3
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; CHECK-NEXT: [[B0:%.*]] = load float, float* [[B]], align 4
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; CHECK-NEXT: [[B1:%.*]] = load float, float* [[P1]], align 4
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; CHECK-NEXT: [[B2:%.*]] = load float, float* [[P2]], align 4
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; CHECK-NEXT: [[B3:%.*]] = load float, float* [[P3]], align 4
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; CHECK-NEXT: [[C0:%.*]] = fcmp uno float [[A0]], [[B0]]
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; CHECK-NEXT: [[C1:%.*]] = fcmp uno float [[B1]], [[A1]]
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; CHECK-NEXT: [[C2:%.*]] = fcmp uno float [[B2]], [[A2]]
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; CHECK-NEXT: [[C3:%.*]] = fcmp uno float [[A3]], [[B3]]
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; CHECK-NEXT: [[D0:%.*]] = insertelement <4 x i1> undef, i1 [[C0]], i32 0
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; CHECK-NEXT: [[D1:%.*]] = insertelement <4 x i1> [[D0]], i1 [[C1]], i32 1
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; CHECK-NEXT: [[D2:%.*]] = insertelement <4 x i1> [[D1]], i1 [[C2]], i32 2
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; CHECK-NEXT: [[D3:%.*]] = insertelement <4 x i1> [[D2]], i1 [[C3]], i32 3
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; CHECK-NEXT: [[R:%.*]] = sext <4 x i1> [[D3]] to <4 x i32>
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[B:%.*]] to <4 x float>*
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; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, <4 x float>* [[TMP1]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = fcmp uno <4 x float> [[TMP2]], [[A:%.*]]
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; CHECK-NEXT: [[R:%.*]] = sext <4 x i1> [[TMP3]] to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> [[R]]
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;
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%a0 = extractelement <4 x float> %a, i32 0
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