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[X86][SSE] Add sdiv by nonuniform constant vector test containing -1/+1 and all-bits style constants
llvm-svn: 339901
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@ -2953,3 +2953,128 @@ define <8 x i16> @combine_vec_sdiv_nonuniform5(<8 x i16> %x) {
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%1 = sdiv <8 x i16> %x, <i16 -510, i16 -24, i16 -23, i16 3, i16 22, i16 25, i16 255, i16 511>
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ret <8 x i16> %1
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}
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define <8 x i16> @combine_vec_sdiv_nonuniform6(<8 x i16> %x) {
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; SSE-LABEL: combine_vec_sdiv_nonuniform6:
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; SSE: # %bb.0:
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; SSE-NEXT: pextrw $5, %xmm0, %eax
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; SSE-NEXT: movswl %ax, %ecx
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; SSE-NEXT: imull $-32639, %ecx, %ecx # imm = 0x8081
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; SSE-NEXT: shrl $16, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: movzwl %cx, %eax
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; SSE-NEXT: sarw $7, %cx
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; SSE-NEXT: shrl $15, %eax
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; SSE-NEXT: addl %ecx, %eax
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; SSE-NEXT: pextrw $2, %xmm0, %ecx
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; SSE-NEXT: movswl %cx, %edx
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; SSE-NEXT: imull $32703, %edx, %edx # imm = 0x7FBF
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; SSE-NEXT: shrl $16, %edx
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; SSE-NEXT: subl %ecx, %edx
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; SSE-NEXT: movzwl %dx, %ecx
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; SSE-NEXT: sarw $8, %dx
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; SSE-NEXT: shrl $15, %ecx
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; SSE-NEXT: addl %edx, %ecx
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; SSE-NEXT: pextrw $1, %xmm0, %edx
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; SSE-NEXT: movl %edx, %esi
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; SSE-NEXT: sarw $15, %si
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; SSE-NEXT: movzwl %si, %esi
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; SSE-NEXT: shrl $7, %esi
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; SSE-NEXT: addl %edx, %esi
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; SSE-NEXT: sarw $9, %si
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; SSE-NEXT: negl %esi
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; SSE-NEXT: pextrw $0, %xmm0, %edx
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; SSE-NEXT: xorl %edi, %edi
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; SSE-NEXT: cmpl $32768, %edx # imm = 0x8000
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; SSE-NEXT: sete %dil
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; SSE-NEXT: movd %edi, %xmm1
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; SSE-NEXT: pinsrw $1, %esi, %xmm1
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; SSE-NEXT: pinsrw $2, %ecx, %xmm1
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; SSE-NEXT: pextrw $3, %xmm0, %ecx
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; SSE-NEXT: negl %ecx
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; SSE-NEXT: pinsrw $3, %ecx, %xmm1
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; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4],xmm1[5,6,7]
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; SSE-NEXT: pinsrw $5, %eax, %xmm1
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; SSE-NEXT: pextrw $6, %xmm0, %eax
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; SSE-NEXT: movl %eax, %ecx
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; SSE-NEXT: sarw $15, %cx
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; SSE-NEXT: movzwl %cx, %ecx
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; SSE-NEXT: shrl $7, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: sarw $9, %cx
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; SSE-NEXT: pinsrw $6, %ecx, %xmm1
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; SSE-NEXT: pextrw $7, %xmm0, %eax
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; SSE-NEXT: cwtl
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; SSE-NEXT: movl %eax, %ecx
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; SSE-NEXT: shll $14, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: movl %ecx, %eax
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; SSE-NEXT: shrl $31, %eax
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; SSE-NEXT: sarl $29, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: pinsrw $7, %ecx, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sdiv_nonuniform6:
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; AVX: # %bb.0:
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; AVX-NEXT: vpextrw $5, %xmm0, %eax
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; AVX-NEXT: movswl %ax, %ecx
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; AVX-NEXT: imull $-32639, %ecx, %ecx # imm = 0x8081
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; AVX-NEXT: shrl $16, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: movzwl %cx, %eax
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; AVX-NEXT: sarw $7, %cx
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; AVX-NEXT: shrl $15, %eax
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; AVX-NEXT: addl %ecx, %eax
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; AVX-NEXT: vpextrw $2, %xmm0, %ecx
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; AVX-NEXT: movswl %cx, %edx
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; AVX-NEXT: imull $32703, %edx, %edx # imm = 0x7FBF
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; AVX-NEXT: shrl $16, %edx
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; AVX-NEXT: subl %ecx, %edx
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; AVX-NEXT: movzwl %dx, %ecx
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; AVX-NEXT: sarw $8, %dx
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; AVX-NEXT: shrl $15, %ecx
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; AVX-NEXT: addl %edx, %ecx
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; AVX-NEXT: vpextrw $1, %xmm0, %edx
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; AVX-NEXT: movl %edx, %esi
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; AVX-NEXT: sarw $15, %si
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; AVX-NEXT: movzwl %si, %esi
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; AVX-NEXT: shrl $7, %esi
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; AVX-NEXT: addl %edx, %esi
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; AVX-NEXT: sarw $9, %si
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; AVX-NEXT: negl %esi
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; AVX-NEXT: vpextrw $0, %xmm0, %edx
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; AVX-NEXT: xorl %edi, %edi
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; AVX-NEXT: cmpl $32768, %edx # imm = 0x8000
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; AVX-NEXT: sete %dil
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; AVX-NEXT: vmovd %edi, %xmm1
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; AVX-NEXT: vpinsrw $1, %esi, %xmm1, %xmm1
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; AVX-NEXT: vpinsrw $2, %ecx, %xmm1, %xmm1
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; AVX-NEXT: vpextrw $3, %xmm0, %ecx
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; AVX-NEXT: negl %ecx
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; AVX-NEXT: vpinsrw $3, %ecx, %xmm1, %xmm1
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; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4],xmm1[5,6,7]
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; AVX-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1
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; AVX-NEXT: vpextrw $6, %xmm0, %eax
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: sarw $15, %cx
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; AVX-NEXT: movzwl %cx, %ecx
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; AVX-NEXT: shrl $7, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: sarw $9, %cx
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; AVX-NEXT: vpinsrw $6, %ecx, %xmm1, %xmm1
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; AVX-NEXT: vpextrw $7, %xmm0, %eax
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; AVX-NEXT: cwtl
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: shll $14, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: movl %ecx, %eax
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; AVX-NEXT: shrl $31, %eax
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; AVX-NEXT: sarl $29, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: vpinsrw $7, %ecx, %xmm1, %xmm0
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; AVX-NEXT: retq
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%1 = sdiv <8 x i16> %x, <i16 -32768, i16 -512, i16 -511, i16 -1, i16 1, i16 255, i16 512, i16 32767>
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ret <8 x i16> %1
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}
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