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Revert my if-conversion cleanup since it caused a bunch of nightly test
regressions. --- Reverse-merging r106939 into '.': U test/CodeGen/Thumb2/thumb2-ifcvt3.ll U lib/CodeGen/IfConversion.cpp llvm-svn: 106951
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@ -186,7 +186,7 @@ namespace {
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SmallVectorImpl<MachineOperand> &Cond,
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SmallSet<unsigned, 4> &Redefs,
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bool IgnoreBr = false);
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void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges = true);
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void MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI);
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bool MeetIfcvtSizeLimit(MachineBasicBlock &BB, unsigned Size) const {
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return Size > 0 && TII->isProfitableToIfCvt(BB, Size);
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@ -1036,10 +1036,6 @@ bool IfConverter::IfConvertSimple(BBInfo &BBI, IfcvtKind Kind) {
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IterIfcvt = false;
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}
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// RemoveExtraEdges won't work if the block has an unanalyzable branch,
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// which is typically the case for IfConvertSimple, so explicitly remove
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// CvtBBI as a successor.
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BBI.BB->removeSuccessor(CvtBBI->BB);
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RemoveExtraEdges(BBI);
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// Update block info. BB can be iteratively if-converted.
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@ -1102,7 +1098,8 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
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InitPredRedefs(NextBBI->BB, Redefs, TRI);
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bool HasEarlyExit = CvtBBI->FalseBB != NULL;
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if (CvtBBI->BB->pred_size() > 1) {
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bool DupBB = CvtBBI->BB->pred_size() > 1;
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if (DupBB) {
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BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
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// Copy instructions in the true block, predicate them, and add them to
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// the entry block.
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@ -1114,7 +1111,7 @@ bool IfConverter::IfConvertTriangle(BBInfo &BBI, IfcvtKind Kind) {
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// Now merge the entry of the triangle with the true block.
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BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
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MergeBlocks(BBI, *CvtBBI, false);
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MergeBlocks(BBI, *CvtBBI);
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}
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// If 'true' block has a 'false' successor, add an exit branch to it.
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@ -1187,9 +1184,9 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
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return false;
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}
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// Put the predicated instructions from the 'true' block before the
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// instructions from the 'false' block, unless the true block would clobber
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// the predicate, in which case, do the opposite.
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// Merge the 'true' and 'false' blocks by copying the instructions
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// from the 'false' block to the 'true' block. That is, unless the true
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// block would clobber the predicate, in that case, do the opposite.
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BBInfo *BBI1 = &TrueBBI;
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BBInfo *BBI2 = &FalseBBI;
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SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
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@ -1279,8 +1276,8 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
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PredicateBlock(*BBI2, DI2, *Cond2, Redefs);
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// Merge the true block into the entry of the diamond.
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MergeBlocks(BBI, *BBI1, TailBB == 0);
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MergeBlocks(BBI, *BBI2, TailBB == 0);
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MergeBlocks(BBI, *BBI1);
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MergeBlocks(BBI, *BBI2);
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// If the if-converted block falls through or unconditionally branches into
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// the tail block, and the tail block does not have other predecessors, then
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@ -1289,20 +1286,15 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
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if (TailBB) {
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BBInfo TailBBI = BBAnalysis[TailBB->getNumber()];
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if (TailBB->pred_size() == 1 && !TailBBI.HasFallThrough) {
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BBI.NonPredSize -= TII->RemoveBranch(*BBI.BB);
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MergeBlocks(BBI, TailBBI);
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TailBBI.IsDone = true;
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} else {
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BBI.BB->addSuccessor(TailBB);
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InsertUncondBranch(BBI.BB, TailBB, TII);
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BBI.HasFallThrough = false;
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}
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}
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// RemoveExtraEdges won't work if the block has an unanalyzable branch,
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// which can happen here if TailBB is unanalyzable and is merged, so
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// explicitly remove BBI1 and BBI2 as successors.
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BBI.BB->removeSuccessor(BBI1->BB);
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BBI.BB->removeSuccessor(BBI2->BB);
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RemoveExtraEdges(BBI);
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// Update block info.
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@ -1375,19 +1367,17 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
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UpdatePredRedefs(MI, Redefs, TRI, true);
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}
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if (!IgnoreBr) {
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std::vector<MachineBasicBlock *> Succs(FromBBI.BB->succ_begin(),
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FromBBI.BB->succ_end());
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MachineBasicBlock *NBB = getNextBlock(FromBBI.BB);
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MachineBasicBlock *FallThrough = FromBBI.HasFallThrough ? NBB : NULL;
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std::vector<MachineBasicBlock *> Succs(FromBBI.BB->succ_begin(),
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FromBBI.BB->succ_end());
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MachineBasicBlock *NBB = getNextBlock(FromBBI.BB);
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MachineBasicBlock *FallThrough = FromBBI.HasFallThrough ? NBB : NULL;
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for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
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MachineBasicBlock *Succ = Succs[i];
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// Fallthrough edge can't be transferred.
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if (Succ == FallThrough)
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continue;
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ToBBI.BB->addSuccessor(Succ);
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}
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for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
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MachineBasicBlock *Succ = Succs[i];
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// Fallthrough edge can't be transferred.
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if (Succ == FallThrough)
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continue;
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ToBBI.BB->addSuccessor(Succ);
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}
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std::copy(FromBBI.Predicate.begin(), FromBBI.Predicate.end(),
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@ -1401,14 +1391,21 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI,
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}
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/// MergeBlocks - Move all instructions from FromBB to the end of ToBB.
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/// This will leave FromBB as an empty block, so remove all of its
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/// successor edges except for the fall-through edge. If AddEdges is true,
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/// i.e., when FromBBI's branch is being moved, add those successor edges to
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/// ToBBI.
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void IfConverter::MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges) {
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///
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void IfConverter::MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI) {
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ToBBI.BB->splice(ToBBI.BB->end(),
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FromBBI.BB, FromBBI.BB->begin(), FromBBI.BB->end());
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// Redirect all branches to FromBB to ToBB.
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std::vector<MachineBasicBlock *> Preds(FromBBI.BB->pred_begin(),
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FromBBI.BB->pred_end());
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for (unsigned i = 0, e = Preds.size(); i != e; ++i) {
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MachineBasicBlock *Pred = Preds[i];
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if (Pred == ToBBI.BB)
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continue;
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Pred->ReplaceUsesOfBlockWith(FromBBI.BB, ToBBI.BB);
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}
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std::vector<MachineBasicBlock *> Succs(FromBBI.BB->succ_begin(),
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FromBBI.BB->succ_end());
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MachineBasicBlock *NBB = getNextBlock(FromBBI.BB);
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@ -1420,8 +1417,7 @@ void IfConverter::MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges) {
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if (Succ == FallThrough)
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continue;
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FromBBI.BB->removeSuccessor(Succ);
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if (AddEdges)
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ToBBI.BB->addSuccessor(Succ);
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ToBBI.BB->addSuccessor(Succ);
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}
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// Now FromBBI always falls through to the next block!
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@ -23,7 +23,7 @@ bb52: ; preds = %newFuncRoot
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; CHECK: movne
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; CHECK: moveq
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; CHECK: pop
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; CHECK-NEXT: @ BB#1:
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; CHECK-NEXT: LBB0_1:
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%0 = load i64* @posed, align 4 ; <i64> [#uses=3]
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%1 = sub i64 %0, %.reload78 ; <i64> [#uses=1]
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%2 = ashr i64 %1, 1 ; <i64> [#uses=3]
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