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[X86] Consider isCodeGenOnly in the EVEX2VEX pass to make VMAXPD/PS map to the non-commutable VEX instruction. Use EVEX2VEX override to fix the scalar instructions.

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Previously the match was ambiguous and VMAXPS/PD and VMAXCPS/PD
were mapped to the same VEX instruction. But we should keep
the commutableness when change the opcode.

llvm-svn: 373303
This commit is contained in:
Craig Topper 2019-10-01 07:10:09 +00:00
parent 46235d2c6f
commit 8b8482596d
3 changed files with 50 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
lib/Target/X86/X86InstrAVX512.td
View File

@ -5303,7 +5303,8 @@ multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo
}
multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
SDNode OpNode, SDNode VecNode, SDNode SaeNode,
X86FoldableSchedWrite sched, bit IsCommutable> {
X86FoldableSchedWrite sched, bit IsCommutable,
string EVEX2VexOvrd> {
let ExeDomain = _.ExeDomain in {
defm rr_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _.RC:$src1, _.RC:$src2), OpcodeStr,
@ -5323,7 +5324,8 @@ multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
(ins _.FRC:$src1, _.FRC:$src2),
OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))]>,
Sched<[sched]> {
Sched<[sched]>,
EVEX2VEXOverride<EVEX2VexOvrd#"rr"> {
let isCommutable = IsCommutable;
}
def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
@ -5331,7 +5333,8 @@ multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[(set _.FRC:$dst, (OpNode _.FRC:$src1,
(_.ScalarLdFrag addr:$src2)))]>,
Sched<[sched.Folded, sched.ReadAfterFold]>;
Sched<[sched.Folded, sched.ReadAfterFold]>,
EVEX2VEXOverride<EVEX2VexOvrd#"rm">;
}
defm rrb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
@ -5361,10 +5364,12 @@ multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
SDNode VecNode, SDNode SaeNode,
X86SchedWriteSizes sched, bit IsCommutable> {
defm SSZ : avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, OpNode,
VecNode, SaeNode, sched.PS.Scl, IsCommutable>,
VecNode, SaeNode, sched.PS.Scl, IsCommutable,
NAME#"SS">,
XS, EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
defm SDZ : avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, OpNode,
VecNode, SaeNode, sched.PD.Scl, IsCommutable>,
VecNode, SaeNode, sched.PD.Scl, IsCommutable,
NAME#"SD">,
XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
}
defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86fadds, X86faddRnds,
@ -5384,13 +5389,14 @@ defm VMAX : avx512_binop_s_sae<0x5F, "vmax", X86fmax, X86fmaxs, X86fmaxSAEs,
// X86fminc and X86fmaxc instead of X86fmin and X86fmax
multiclass avx512_comutable_binop_s<bits<8> opc, string OpcodeStr,
X86VectorVTInfo _, SDNode OpNode,
X86FoldableSchedWrite sched> {
X86FoldableSchedWrite sched,
string EVEX2VEXOvrd> {
let isCodeGenOnly = 1, Predicates = [HasAVX512], ExeDomain = _.ExeDomain in {
def rr : I< opc, MRMSrcReg, (outs _.FRC:$dst),
(ins _.FRC:$src1, _.FRC:$src2),
OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))]>,
Sched<[sched]> {
Sched<[sched]>, EVEX2VEXOverride<EVEX2VEXOvrd#"rr"> {
let isCommutable = 1;
}
def rm : I< opc, MRMSrcMem, (outs _.FRC:$dst),
@ -5398,24 +5404,27 @@ multiclass avx512_comutable_binop_s<bits<8> opc, string OpcodeStr,
OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[(set _.FRC:$dst, (OpNode _.FRC:$src1,
(_.ScalarLdFrag addr:$src2)))]>,
Sched<[sched.Folded, sched.ReadAfterFold]>;
Sched<[sched.Folded, sched.ReadAfterFold]>,
EVEX2VEXOverride<EVEX2VEXOvrd#"rm">;
}
}
defm VMINCSSZ : avx512_comutable_binop_s<0x5D, "vminss", f32x_info, X86fminc,
SchedWriteFCmp.Scl>, XS, EVEX_4V,
VEX_LIG, EVEX_CD8<32, CD8VT1>;
SchedWriteFCmp.Scl, "VMINCSS">, XS,
EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
defm VMINCSDZ : avx512_comutable_binop_s<0x5D, "vminsd", f64x_info, X86fminc,
SchedWriteFCmp.Scl>, XD, VEX_W, EVEX_4V,
VEX_LIG, EVEX_CD8<64, CD8VT1>;
SchedWriteFCmp.Scl, "VMINCSD">, XD,
VEX_W, EVEX_4V, VEX_LIG,
EVEX_CD8<64, CD8VT1>;
defm VMAXCSSZ : avx512_comutable_binop_s<0x5F, "vmaxss", f32x_info, X86fmaxc,
SchedWriteFCmp.Scl>, XS, EVEX_4V,
VEX_LIG, EVEX_CD8<32, CD8VT1>;
SchedWriteFCmp.Scl, "VMAXCSS">, XS,
EVEX_4V, VEX_LIG, EVEX_CD8<32, CD8VT1>;
defm VMAXCSDZ : avx512_comutable_binop_s<0x5F, "vmaxsd", f64x_info, X86fmaxc,
SchedWriteFCmp.Scl>, XD, VEX_W, EVEX_4V,
VEX_LIG, EVEX_CD8<64, CD8VT1>;
SchedWriteFCmp.Scl, "VMAXCSD">, XD,
VEX_W, EVEX_4V, VEX_LIG,
EVEX_CD8<64, CD8VT1>;
multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDPatternOperator OpNode,
X86VectorVTInfo _, X86FoldableSchedWrite sched,

48
test/CodeGen/X86/evex-to-vex-compress.mir
View File

@ -355,13 +355,13 @@ body: |
$ymm0 = VMAXCPSZ256rm $ymm0, $rip, 1, $rax, 0, $noreg
; CHECK: $ymm0 = VMAXCPSYrr $ymm0, $ymm1
$ymm0 = VMAXCPSZ256rr $ymm0, $ymm1
; CHECK: $ymm0 = VMAXCPDYrm $ymm0, $rip, 1, $rax, 0, $noreg
; CHECK: $ymm0 = VMAXPDYrm $ymm0, $rip, 1, $rax, 0, $noreg
$ymm0 = VMAXPDZ256rm $ymm0, $rip, 1, $rax, 0, $noreg
; CHECK: $ymm0 = VMAXCPDYrr $ymm0, $ymm1
; CHECK: $ymm0 = VMAXPDYrr $ymm0, $ymm1
$ymm0 = VMAXPDZ256rr $ymm0, $ymm1
; CHECK: $ymm0 = VMAXCPSYrm $ymm0, $rip, 1, $rax, 0, $noreg
; CHECK: $ymm0 = VMAXPSYrm $ymm0, $rip, 1, $rax, 0, $noreg
$ymm0 = VMAXPSZ256rm $ymm0, $rip, 1, $rax, 0, $noreg
; CHECK: $ymm0 = VMAXCPSYrr $ymm0, $ymm1
; CHECK: $ymm0 = VMAXPSYrr $ymm0, $ymm1
$ymm0 = VMAXPSZ256rr $ymm0, $ymm1
; CHECK: $ymm0 = VMINCPDYrm $ymm0, $rip, 1, $rax, 0, $noreg
$ymm0 = VMINCPDZ256rm $ymm0, $rip, 1, $rax, 0, $noreg
@ -371,13 +371,13 @@ body: |
$ymm0 = VMINCPSZ256rm $ymm0, $rip, 1, $rax, 0, $noreg
; CHECK: $ymm0 = VMINCPSYrr $ymm0, $ymm1
$ymm0 = VMINCPSZ256rr $ymm0, $ymm1
; CHECK: $ymm0 = VMINCPDYrm $ymm0, $rip, 1, $rax, 0, $noreg
; CHECK: $ymm0 = VMINPDYrm $ymm0, $rip, 1, $rax, 0, $noreg
$ymm0 = VMINPDZ256rm $ymm0, $rip, 1, $rax, 0, $noreg
; CHECK: $ymm0 = VMINCPDYrr $ymm0, $ymm1
; CHECK: $ymm0 = VMINPDYrr $ymm0, $ymm1
$ymm0 = VMINPDZ256rr $ymm0, $ymm1
; CHECK: $ymm0 = VMINCPSYrm $ymm0, $rip, 1, $rax, 0, $noreg
; CHECK: $ymm0 = VMINPSYrm $ymm0, $rip, 1, $rax, 0, $noreg
$ymm0 = VMINPSZ256rm $ymm0, $rip, 1, $rax, 0, $noreg
; CHECK: $ymm0 = VMINCPSYrr $ymm0, $ymm1
; CHECK: $ymm0 = VMINPSYrr $ymm0, $ymm1
$ymm0 = VMINPSZ256rr $ymm0, $ymm1
; CHECK: $ymm0 = VXORPDYrm $ymm0, $rip, 1, $rax, 0, $noreg
$ymm0 = VXORPDZ256rm $ymm0, $rip, 1, $rax, 0, $noreg
@ -1083,13 +1083,13 @@ body: |
$xmm0 = VMAXCPSZ128rm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMAXCPSrr $xmm0, $xmm1
$xmm0 = VMAXCPSZ128rr $xmm0, $xmm1
; CHECK: $xmm0 = VMAXCPDrm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMAXPDrm $xmm0, $rip, 1, $rax, 0, $noreg
$xmm0 = VMAXPDZ128rm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMAXCPDrr $xmm0, $xmm1
; CHECK: $xmm0 = VMAXPDrr $xmm0, $xmm1
$xmm0 = VMAXPDZ128rr $xmm0, $xmm1
; CHECK: $xmm0 = VMAXCPSrm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMAXPSrm $xmm0, $rip, 1, $rax, 0, $noreg
$xmm0 = VMAXPSZ128rm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMAXCPSrr $xmm0, $xmm1
; CHECK: $xmm0 = VMAXPSrr $xmm0, $xmm1
$xmm0 = VMAXPSZ128rr $xmm0, $xmm1
; CHECK: $xmm0 = VMINCPDrm $xmm0, $rip, 1, $rax, 0, $noreg
$xmm0 = VMINCPDZ128rm $xmm0, $rip, 1, $rax, 0, $noreg
@ -1099,13 +1099,13 @@ body: |
$xmm0 = VMINCPSZ128rm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMINCPSrr $xmm0, $xmm1
$xmm0 = VMINCPSZ128rr $xmm0, $xmm1
; CHECK: $xmm0 = VMINCPDrm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMINPDrm $xmm0, $rip, 1, $rax, 0, $noreg
$xmm0 = VMINPDZ128rm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMINCPDrr $xmm0, $xmm1
; CHECK: $xmm0 = VMINPDrr $xmm0, $xmm1
$xmm0 = VMINPDZ128rr $xmm0, $xmm1
; CHECK: $xmm0 = VMINCPSrm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMINPSrm $xmm0, $rip, 1, $rax, 0, $noreg
$xmm0 = VMINPSZ128rm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMINCPSrr $xmm0, $xmm1
; CHECK: $xmm0 = VMINPSrr $xmm0, $xmm1
$xmm0 = VMINPSZ128rr $xmm0, $xmm1
; CHECK: $xmm0 = VMULPDrm $xmm0, $rip, 1, $rax, 0, $noreg
$xmm0 = VMULPDZ128rm $xmm0, $rip, 1, $rax, 0, $noreg
@ -1850,19 +1850,19 @@ body: |
$xmm0 = VMAXCSSZrm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMAXCSSrr $xmm0, $xmm1
$xmm0 = VMAXCSSZrr $xmm0, $xmm1
; CHECK: $xmm0 = VMAXCSDrm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMAXSDrm $xmm0, $rip, 1, $rax, 0, $noreg
$xmm0 = VMAXSDZrm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMAXSDrm_Int $xmm0, $rip, 1, $rax, 0, $noreg
$xmm0 = VMAXSDZrm_Int $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMAXCSDrr $xmm0, $xmm1
; CHECK: $xmm0 = VMAXSDrr $xmm0, $xmm1
$xmm0 = VMAXSDZrr $xmm0, $xmm1
; CHECK: $xmm0 = VMAXSDrr_Int $xmm0, $xmm1
$xmm0 = VMAXSDZrr_Int $xmm0, $xmm1
; CHECK: $xmm0 = VMAXCSSrm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMAXSSrm $xmm0, $rip, 1, $rax, 0, $noreg
$xmm0 = VMAXSSZrm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMAXSSrm_Int $xmm0, $rip, 1, $rax, 0, $noreg
$xmm0 = VMAXSSZrm_Int $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMAXCSSrr $xmm0, $xmm1
; CHECK: $xmm0 = VMAXSSrr $xmm0, $xmm1
$xmm0 = VMAXSSZrr $xmm0, $xmm1
; CHECK: $xmm0 = VMAXSSrr_Int $xmm0, $xmm1
$xmm0 = VMAXSSZrr_Int $xmm0, $xmm1
@ -1874,19 +1874,19 @@ body: |
$xmm0 = VMINCSSZrm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMINCSSrr $xmm0, $xmm1
$xmm0 = VMINCSSZrr $xmm0, $xmm1
; CHECK: $xmm0 = VMINCSDrm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMINSDrm $xmm0, $rip, 1, $rax, 0, $noreg
$xmm0 = VMINSDZrm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMINSDrm_Int $xmm0, $rip, 1, $rax, 0, $noreg
$xmm0 = VMINSDZrm_Int $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMINCSDrr $xmm0, $xmm1
; CHECK: $xmm0 = VMINSDrr $xmm0, $xmm1
$xmm0 = VMINSDZrr $xmm0, $xmm1
; CHECK: $xmm0 = VMINSDrr_Int $xmm0, $xmm1
$xmm0 = VMINSDZrr_Int $xmm0, $xmm1
; CHECK: $xmm0 = VMINCSSrm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMINSSrm $xmm0, $rip, 1, $rax, 0, $noreg
$xmm0 = VMINSSZrm $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMINSSrm_Int $xmm0, $rip, 1, $rax, 0, $noreg
$xmm0 = VMINSSZrm_Int $xmm0, $rip, 1, $rax, 0, $noreg
; CHECK: $xmm0 = VMINCSSrr $xmm0, $xmm1
; CHECK: $xmm0 = VMINSSrr $xmm0, $xmm1
$xmm0 = VMINSSZrr $xmm0, $xmm1
; CHECK: $xmm0 = VMINSSrr_Int $xmm0, $xmm1
$xmm0 = VMINSSZrr_Int $xmm0, $xmm1

1
utils/TableGen/X86EVEX2VEXTablesEmitter.cpp
View File

@ -98,6 +98,7 @@ public:
bool EVEX_W1_VEX_W0 = RecE->getValueAsBit("EVEX_W1_VEX_W0");
if (RecV->getValueAsDef("OpEnc")->getName().str() != "EncVEX" ||
RecV->getValueAsBit("isCodeGenOnly") != RecE->getValueAsBit("isCodeGenOnly") ||
// VEX/EVEX fields
RecV->getValueAsDef("OpPrefix") != RecE->getValueAsDef("OpPrefix") ||
RecV->getValueAsDef("OpMap") != RecE->getValueAsDef("OpMap") ||