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ARM stm/ldm instructions require more than one register in the register list.
Otherwise, a plain str/ldr should be used instead. Make sure we account for that in prologue/epilogue code generation. rdar://8745460 llvm-svn: 121391
This commit is contained in:
Jim Grosbach
parent
bd5b0c9ec6
commit
8bc33cc6e5
@ -12,6 +12,7 @@
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//===----------------------------------------------------------------------===//
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#include "ARMFrameInfo.h"
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#include "ARMAddressingModes.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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@ -501,7 +502,7 @@ int ARMFrameInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
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void ARMFrameInfo::emitPushInst(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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unsigned Opc, bool NoGap,
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unsigned StmOpc, unsigned StrOpc, bool NoGap,
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bool(*Func)(unsigned, bool)) const {
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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@ -540,21 +541,37 @@ void ARMFrameInfo::emitPushInst(MachineBasicBlock &MBB,
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Regs.push_back(std::make_pair(Reg, isKill));
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}
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if (!Regs.empty()) {
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if (Regs.empty())
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continue;
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if (Regs.size() > 1 || StrOpc== 0) {
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MachineInstrBuilder MIB =
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AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
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AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
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.addReg(ARM::SP));
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for (unsigned i = 0, e = Regs.size(); i < e; ++i)
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MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
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Regs.clear();
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} else if (Regs.size() == 1) {
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MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
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ARM::SP)
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.addReg(Regs[0].first, getKillRegState(Regs[0].second))
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.addReg(ARM::SP);
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// ARM mode needs an extra reg0 here due to addrmode2. Will go away once
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// that refactoring is complete (eventually).
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if (StrOpc == ARM::STR_PRE) {
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MIB.addReg(0);
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MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::sub, 4, ARM_AM::no_shift));
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} else
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MIB.addImm(-4);
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AddDefaultPred(MIB);
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}
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Regs.clear();
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}
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}
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void ARMFrameInfo::emitPopInst(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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unsigned Opc, bool isVarArg, bool NoGap,
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unsigned LdmOpc, unsigned LdrOpc,
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bool isVarArg, bool NoGap,
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bool(*Func)(unsigned, bool)) const {
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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@ -572,7 +589,7 @@ void ARMFrameInfo::emitPopInst(MachineBasicBlock &MBB,
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if (Reg == ARM::LR && !isVarArg) {
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Reg = ARM::PC;
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Opc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
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LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET;
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// Fold the return instruction into the LDM.
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DeleteRet = true;
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}
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@ -587,17 +604,36 @@ void ARMFrameInfo::emitPopInst(MachineBasicBlock &MBB,
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Regs.push_back(Reg);
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}
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if (!Regs.empty()) {
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if (Regs.empty())
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continue;
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if (Regs.size() > 1 || LdrOpc == 0) {
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MachineInstrBuilder MIB =
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AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
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AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
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.addReg(ARM::SP));
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for (unsigned i = 0, e = Regs.size(); i < e; ++i)
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MIB.addReg(Regs[i], getDefRegState(true));
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if (DeleteRet)
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MI->eraseFromParent();
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MI = MIB;
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Regs.clear();
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} else if (Regs.size() == 1) {
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// If we adjusted the reg to PC from LR above, switch it back here. We
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// only do that for LDM.
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if (Regs[0] == ARM::PC)
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Regs[0] = ARM::LR;
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MachineInstrBuilder MIB =
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BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
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.addReg(ARM::SP, RegState::Define)
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.addReg(ARM::SP);
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// ARM mode needs an extra reg0 here due to addrmode2. Will go away once
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// that refactoring is complete (eventually).
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if (LdrOpc == ARM::LDR_POST) {
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MIB.addReg(0);
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MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
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} else
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MIB.addImm(4);
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AddDefaultPred(MIB);
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}
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Regs.clear();
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}
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}
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@ -613,10 +649,11 @@ bool ARMFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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DebugLoc DL = MI->getDebugLoc();
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unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD;
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unsigned PushOneOpc = AFI->isThumbFunction() ? ARM::t2STR_PRE : ARM::STR_PRE;
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unsigned FltOpc = ARM::VSTMDDB_UPD;
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emitPushInst(MBB, MI, CSI, PushOpc, false, &isARMArea1Register);
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emitPushInst(MBB, MI, CSI, PushOpc, false, &isARMArea2Register);
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emitPushInst(MBB, MI, CSI, FltOpc, true, &isARMArea3Register);
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emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register);
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emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register);
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emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register);
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return true;
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}
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@ -634,10 +671,13 @@ bool ARMFrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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DebugLoc DL = MI->getDebugLoc();
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unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD;
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unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST : ARM::LDR_POST;
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unsigned FltOpc = ARM::VLDMDIA_UPD;
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emitPopInst(MBB, MI, CSI, FltOpc, isVarArg, true, &isARMArea3Register);
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emitPopInst(MBB, MI, CSI, PopOpc, isVarArg, false, &isARMArea2Register);
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emitPopInst(MBB, MI, CSI, PopOpc, isVarArg, false, &isARMArea1Register);
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emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register);
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emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
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&isARMArea2Register);
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emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
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&isARMArea1Register);
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return true;
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}
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@ -59,11 +59,12 @@ public:
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private:
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void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI, unsigned Opc,
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bool NoGap, bool(*Func)(unsigned, bool)) const;
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const std::vector<CalleeSavedInfo> &CSI, unsigned StmOpc,
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unsigned StrOpc, bool NoGap,
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bool(*Func)(unsigned, bool)) const;
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void emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI, unsigned Opc,
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bool isVarArg, bool NoGap,
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const std::vector<CalleeSavedInfo> &CSI, unsigned LdmOpc,
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unsigned LdrOpc, bool isVarArg, bool NoGap,
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bool(*Func)(unsigned, bool)) const;
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};
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@ -4,8 +4,8 @@
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define i64 @t(i64 %a) nounwind readonly {
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entry:
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; CHECK: push {lr}
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; CHECK: ldmia sp!, {pc}
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; CHECK: str lr, [sp, #-4]!
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; CHECK: ldr lr, [sp], #4
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%0 = load i64** @b, align 4
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%1 = load i64* %0, align 4
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%2 = mul i64 %1, %a
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@ -39,7 +39,7 @@ entry:
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; CHECK: ittt eq
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; CHECK: moveq r0
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; CHECK-NOT: LBB0_
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; CHECK: popeq
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; CHECK: ldreq
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; CHECK: popeq
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switch i32 undef, label %bb7 [
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i32 37, label %bb43
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