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Handle 64-bit floating point binops as well.

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llvm-svn: 113461
This commit is contained in:
Eric Christopher 2010-09-09 01:02:03 +00:00
parent f2f2b06719
commit 8c3a582b5f
1 changed files with 12 additions and 10 deletions
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22
lib/Target/ARM/ARMFastISel.cpp
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@ -742,16 +742,16 @@ bool ARMFastISel::ARMSelectFPExt(const Instruction *I) {
} }
bool ARMFastISel::ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode) { bool ARMFastISel::ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
EVT VT = TLI.getValueType(I->getType(), true);
// We can get here in the case when we want to use NEON for our fp // We can get here in the case when we want to use NEON for our fp
// operations, but can't figure out how to. Just use the vfp instructions // operations, but can't figure out how to. Just use the vfp instructions
// if we have them. // if we have them.
// FIXME: It'd be nice to use NEON instructions. // FIXME: It'd be nice to use NEON instructions.
if (!Subtarget->hasVFP2()) return false; const Type *Ty = I->getType();
bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
EVT VT = TLI.getValueType(I->getType(), true); if (isFloat && !Subtarget->hasVFP2())
return false;
// In this case make extra sure we have a 32-bit floating point add.
if (VT != MVT::f32) return false;
unsigned Op1 = getRegForValue(I->getOperand(0)); unsigned Op1 = getRegForValue(I->getOperand(0));
if (Op1 == 0) return false; if (Op1 == 0) return false;
@ -760,19 +760,21 @@ bool ARMFastISel::ARMSelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
if (Op2 == 0) return false; if (Op2 == 0) return false;
unsigned Opc; unsigned Opc;
bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
VT.getSimpleVT().SimpleTy == MVT::i64;
switch (ISDOpcode) { switch (ISDOpcode) {
default: return false; default: return false;
case ISD::FADD: case ISD::FADD:
Opc = ARM::VADDS; Opc = is64bit ? ARM::VADDD : ARM::VADDS;
break; break;
case ISD::FSUB: case ISD::FSUB:
Opc = ARM::VSUBS; Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
break; break;
case ISD::FMUL: case ISD::FMUL:
Opc = ARM::VMULS; Opc = is64bit ? ARM::VMULD : ARM::VMULS;
break; break;
} }
unsigned ResultReg = createResultReg(ARM::SPRRegisterClass); unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(Opc), ResultReg) TII.get(Opc), ResultReg)
.addReg(Op1).addReg(Op2)); .addReg(Op1).addReg(Op2));