RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 03:53:04 +02:00
Code Issues Projects Releases Wiki Activity

Stub for constant shift expr support.

Browse Source 
llvm-svn: 10168
This commit is contained in:
Brian Gaeke 2003-11-22 05:18:35 +00:00
parent 17db893394
commit 8c4c9f6f1e
1 changed files with 23 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
lib/Target/X86/InstSelectSimple.cpp
View File

@ -224,6 +224,13 @@ namespace {
MachineBasicBlock::iterator &IP,
Value *Op0, Value *Op1, unsigned Opcode,
unsigned TargetReg);
/// emitShiftOperation - Common code shared between visitShiftInst and
/// constant expression support.
void emitShiftOperation(MachineBasicBlock *BB,
MachineBasicBlock::iterator &IP,
Value *Op0, Value *Op1, unsigned Opcode,
unsigned TargetReg);
/// copyConstantToRegister - Output the instructions required to put the
@ -384,6 +391,12 @@ void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
CE->getOpcode(), R);
return;
case Instruction::Shl:
case Instruction::Shr:
emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
CE->getOpcode(), R);
break;
default:
std::cerr << "Offending expr: " << C << "\n";
assert(0 && "Constant expression not yet handled!\n");
@ -1568,6 +1581,16 @@ void ISel::visitShiftInst(ShiftInst &I) {
}
}
/// emitShiftOperation - Common code shared between visitShiftInst and
/// constant expression support.
void ISel::emitShiftOperation(MachineBasicBlock *MBB,
MachineBasicBlock::iterator &IP,
Value *Op0, Value *Op1, unsigned Opcode,
unsigned TargetReg) {
// FIXME: Should do all the stuff from visitShiftInst, but use BMI
assert (0 && "Constant shift operations not yet handled");
}
/// visitLoadInst - Implement LLVM load instructions in terms of the x86 'mov'
/// instruction. The load and store instructions are the only place where we