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Update test to match output of optimize compares for ARM.
llvm-svn: 110765
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@ -24,8 +24,7 @@ define i32 @f2(i64 %x, i64 %y) {
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; CHECK: f2
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; CHECK: mov r0, r0, lsr r2
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; CHECK-NEXT: rsb r3, r2, #32
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; CHECK-NEXT: sub r2, r2, #32
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: subs r2, r2, #32
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; CHECK-NEXT: orr r0, r0, r1, lsl r3
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; CHECK-NEXT: movge r0, r1, asr r2
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%a = ashr i64 %x, %y
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@ -37,8 +36,7 @@ define i32 @f3(i64 %x, i64 %y) {
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; CHECK: f3
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; CHECK: mov r0, r0, lsr r2
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; CHECK-NEXT: rsb r3, r2, #32
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; CHECK-NEXT: sub r2, r2, #32
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: subs r2, r2, #32
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; CHECK-NEXT: orr r0, r0, r1, lsl r3
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; CHECK-NEXT: movge r0, r1, lsr r2
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%a = lshr i64 %x, %y
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